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Stefan Roese13b4f632012-08-14 15:04:19 +02001/*
Stefan Roese8aa34492013-04-25 23:20:23 +00002 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
Stefan Roese13b4f632012-08-14 15:04:19 +02003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese13b4f632012-08-14 15:04:19 +02005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
11 * High Level Configuration Options
12 * (easy to change)
13 */
14
15#define CONFIG_MPC5200
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090016#define CONFIG_A3M071 /* A3M071 board */
Stefan Roesec07e8da2014-11-19 09:37:47 +010017#define CONFIG_DISPLAY_BOARDINFO
18#define CONFIG_SYS_GENERIC_BOARD
Stefan Roese13b4f632012-08-14 15:04:19 +020019
20#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
21
Stefan Roesed4451d32013-02-07 02:10:11 +000022#define CONFIG_SPL_TARGET "u-boot-img.bin"
23
Stefan Roese13b4f632012-08-14 15:04:19 +020024#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
25
26#define CONFIG_MISC_INIT_R
27#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
28
Stefan Roesed4451d32013-02-07 02:10:11 +000029#ifdef CONFIG_A4M2K
30#define CONFIG_HOSTNAME a4m2k
31#else
32#define CONFIG_HOSTNAME a3m071
33#endif
34
Stefan Roesed62a89b2013-06-22 16:16:25 +020035#define CONFIG_BOOTCOUNT_LIMIT
36
Stefan Roese13b4f632012-08-14 15:04:19 +020037/*
38 * Serial console configuration
39 */
40#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
41#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
42#define CONFIG_SYS_BAUDRATE_TABLE \
43 { 9600, 19200, 38400, 57600, 115200, 230400 }
44
45/*
46 * Command line configuration.
47 */
48#include <config_cmd_default.h>
49
50#define CONFIG_CMD_BSP
51#define CONFIG_CMD_CACHE
Stefan Roese13b4f632012-08-14 15:04:19 +020052#define CONFIG_CMD_MII
53#define CONFIG_CMD_REGINFO
Stefan Roese8aa34492013-04-25 23:20:23 +000054#define CONFIG_CMD_DHCP
55#define CONFIG_BOOTP_SEND_HOSTNAME
56#define CONFIG_BOOTP_SERVERIP
57#define CONFIG_BOOTP_MAY_FAIL
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_GATEWAY
60#define CONFIG_BOOTP_SERVERIP
61#define CONFIG_NET_RETRY_COUNT 3
62#define CONFIG_CMD_LINK_LOCAL
Przemyslaw Marczak3c1c68c2014-03-25 10:58:19 +010063#define CONFIG_LIB_RAND
Stefan Roese8aa34492013-04-25 23:20:23 +000064#define CONFIG_NETCONSOLE
65#define CONFIG_SYS_CONSOLE_IS_IN_ENV
66#define CONFIG_CMD_PING
67#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
68#define CONFIG_MTD_PARTITIONS /* needed for UBI */
69#define CONFIG_FLASH_CFI_MTD
70#define MTDIDS_DEFAULT "nor0=fc000000.flash"
71#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020072 "128k(env1)," \
73 "128k(env2)," \
Stefan Roese8aa34492013-04-25 23:20:23 +000074 "128k(hwinfo)," \
75 "1M(nvramsim)," \
76 "128k(dtb)," \
77 "5M(kernel)," \
78 "128k(sysinfo)," \
79 "7552k(root)," \
80 "4M(app)," \
Stefan Roesed62a89b2013-06-22 16:16:25 +020081 "5376k(data)," \
82 "8M(install)"
83
Stefan Roese8aa34492013-04-25 23:20:23 +000084#define CONFIG_LZO /* needed for UBI */
85#define CONFIG_RBTREE /* needed for UBI */
86#define CONFIG_CMD_MTDPARTS
87#define CONFIG_CMD_UBI
88#define CONFIG_CMD_UBIFS
89#define CONFIG_FIT
Stefan Roese13b4f632012-08-14 15:04:19 +020090
91/*
92 * IPB Bus clocking configuration.
93 */
94#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
95/* define for 66MHz speed - undef for 33MHz PCI clock speed */
Stefan Roesed4451d32013-02-07 02:10:11 +000096#ifdef CONFIG_A4M2K
97#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
98#else
Stefan Roese13b4f632012-08-14 15:04:19 +020099#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Stefan Roesed4451d32013-02-07 02:10:11 +0000100#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200101
102/* pass open firmware flat tree */
103#define CONFIG_OF_LIBFDT
104#define CONFIG_OF_BOARD_SETUP
105
106/* maximum size of the flat tree (8K) */
107#define OF_FLAT_TREE_MAX_SIZE 8192
108
109#define OF_CPU "PowerPC,5200@0"
110#define OF_SOC "soc5200@f0000000"
111#define OF_TBCLK (bd->bi_busfreq / 4)
112#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
113
114/*
Stefan Roese13b4f632012-08-14 15:04:19 +0200115 * NOR flash configuration
116 */
117#define CONFIG_SYS_FLASH_BASE 0xfc000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000118#define CONFIG_SYS_FLASH_SIZE 0x02000000
Stefan Roese8aa34492013-04-25 23:20:23 +0000119#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
Stefan Roese13b4f632012-08-14 15:04:19 +0200120
121#define CONFIG_SYS_MAX_FLASH_BANKS 1
122#define CONFIG_SYS_MAX_FLASH_SECT 256
123#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
124#define CONFIG_SYS_FLASH_WRITE_TOUT 500
125#define CONFIG_SYS_FLASH_LOCK_TOUT 5
126#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
127#define CONFIG_SYS_FLASH_PROTECTION
128#define CONFIG_FLASH_CFI_DRIVER
129#define CONFIG_SYS_FLASH_CFI
130#define CONFIG_SYS_FLASH_EMPTY_INFO
131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Stefan Roesef8945512013-04-04 03:55:42 +0000132#define CONFIG_FLASH_VERIFY
Stefan Roese13b4f632012-08-14 15:04:19 +0200133
134/*
135 * Environment settings
136 */
137#define CONFIG_ENV_IS_IN_FLASH
138#define CONFIG_ENV_SIZE 0x10000
139#define CONFIG_ENV_SECT_SIZE 0x20000
140#define CONFIG_ENV_OVERWRITE
Stefan Roese8aa34492013-04-25 23:20:23 +0000141#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
142#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200143
144/*
145 * Memory map
146 */
147#define CONFIG_SYS_MBAR 0xf0000000
148#define CONFIG_SYS_SDRAM_BASE 0x00000000
149#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
150
151/* Use SRAM until RAM will be available */
152#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
153#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
154
Stefan Roese13b4f632012-08-14 15:04:19 +0200155#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
Stefan Roese704afcc2013-04-25 23:10:02 +0000156 GENERATED_GBL_DATA_SIZE)
Stefan Roese13b4f632012-08-14 15:04:19 +0200157#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
158
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
160
Stefan Roese8aa34492013-04-25 23:20:23 +0000161#define CONFIG_SYS_MONITOR_LEN (512 << 10)
162#define CONFIG_SYS_MALLOC_LEN (4 << 20)
Stefan Roese13b4f632012-08-14 15:04:19 +0200163#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
164
165/*
166 * Ethernet configuration
167 */
168#define CONFIG_MPC5xxx_FEC
169#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roesed4451d32013-02-07 02:10:11 +0000170#ifdef CONFIG_A4M2K
171#define CONFIG_PHY_ADDR 0x01
172#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200173#define CONFIG_PHY_ADDR 0x00
Stefan Roesed4451d32013-02-07 02:10:11 +0000174#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200175
176/*
177 * GPIO configuration
178 */
179
180/*
181 * GPIO-config depends on failsave-level
182 * failsave 0 means just MPX-config, no digiboard, no fpga
183 * 1 means digiboard ok
184 * 2 means fpga ok
185 */
186
Stefan Roesed4451d32013-02-07 02:10:11 +0000187#ifdef CONFIG_A4M2K
Stefan Roese8aa34492013-04-25 23:20:23 +0000188#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805
Stefan Roesed4451d32013-02-07 02:10:11 +0000189#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200190/* for failsave-level 0 - full failsave */
191#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
192/* for failsave-level 1 - only digiboard ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000193#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065
Stefan Roese13b4f632012-08-14 15:04:19 +0200194/* for failsave-level 2 - all ok */
Stefan Roese8aa34492013-04-25 23:20:23 +0000195#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065
Stefan Roesed4451d32013-02-07 02:10:11 +0000196#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200197
Stefan Roeseaed75482013-02-07 02:10:28 +0000198#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7
199#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
200#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */
201#endif
202
Stefan Roese13b4f632012-08-14 15:04:19 +0200203/*
204 * Configuration matrix
Stefan Roese8aa34492013-04-25 23:20:23 +0000205 * MSB LSB
Stefan Roesed4451d32013-02-07 02:10:11 +0000206 * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
Stefan Roese8aa34492013-04-25 23:20:23 +0000207 * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok )
208 * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok )
Stefan Roese13b4f632012-08-14 15:04:19 +0200209 * || ||| || | ||| | | | |
210 * || ||| || | ||| | | | | bit rev name
211 * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
212 * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
213 * ||| || | ||| | | | | 2 29 ALTs
214 * +++-++--+---+++-+---+---+---+- 3 28 ALTs
215 * ++-++--+---+++-+---+---+---+- 4 27 CS7
216 * +-++--+---+++-+---+---+---+- 5 26 CS6
217 * || | ||| | | | | 6 25 ATA
218 * ++--+---+++-+---+---+---+- 7 24 ATA
219 * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
220 * | ||| | | | | 9 22 IRDA
221 * | ||| | | | | 10 21 IRDA
222 * +---+++-+---+---+---+- 11 20 IRDA
223 * ||| | | | | 12 19 Ether
224 * ||| | | | | 13 18 Ether
225 * ||| | | | | 14 17 Ether
226 * +++-+---+---+---+- 15 16 Ether
227 * ++-+---+---+---+- 16 15 PCI_DIS
228 * +-+---+---+---+- 17 14 USB_SE
229 * | | | | 18 13 USB
230 * +---+---+---+- 19 12 USB
231 * | | | 20 11 PSC3
232 * | | | 21 10 PSC3
233 * | | | 22 9 PSC3
234 * +---+---+- 23 8 PSC3
235 * | | 24 7 -
236 * | | 25 6 PSC2
237 * | | 26 5 PSC2
238 * +---+- 27 4 PSC2
239 * | 28 3 -
240 * | 29 2 PSC1
241 * | 30 1 PSC1
242 * +- 31 0 PSC1
243 */
244
245
246/*
247 * Miscellaneous configurable options
248 */
249#define CONFIG_SYS_LONGHELP
Stefan Roese13b4f632012-08-14 15:04:19 +0200250
251#define CONFIG_CMDLINE_EDITING
252#define CONFIG_SYS_HUSH_PARSER
253#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
254
255#if defined(CONFIG_CMD_KGDB)
256#define CONFIG_SYS_CBSIZE 1024
257#else
258#define CONFIG_SYS_CBSIZE 256
259#endif
260#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
261#define CONFIG_SYS_MAXARGS 16
262#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
263
264#define CONFIG_SYS_MEMTEST_START 0x00100000
265#define CONFIG_SYS_MEMTEST_END 0x00f00000
266
267#define CONFIG_SYS_LOAD_ADDR 0x00100000
268
Stefan Roese13b4f632012-08-14 15:04:19 +0200269#define CONFIG_LOOPW
270#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
271
272/*
273 * Various low-level settings
274 */
275#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
276#define CONFIG_SYS_HID0_FINAL HID0_ICE
277
278#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
279#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
280#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
281#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roesed4451d32013-02-07 02:10:11 +0000282
283#ifdef CONFIG_A4M2K
284/* external MRAM */
285#define CONFIG_SYS_CS1_START 0xf1000000
286#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
287#endif
288
Stefan Roese13b4f632012-08-14 15:04:19 +0200289#define CONFIG_SYS_CS2_START 0xe0000000
290#define CONFIG_SYS_CS2_SIZE 0x00100000
291
Stefan Roesed4451d32013-02-07 02:10:11 +0000292/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200293#define CONFIG_SYS_CS3_START 0xE9000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000294#ifdef CONFIG_A4M2K
295#define CONFIG_SYS_CS3_SIZE 0x00100000
296#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200297#define CONFIG_SYS_CS3_SIZE 0x00080000
Stefan Roesed4451d32013-02-07 02:10:11 +0000298#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200299/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
300#define CONFIG_SYS_CS3_CFG 0x0032B900
301
Stefan Roesed4451d32013-02-07 02:10:11 +0000302#ifndef CONFIG_A4M2K
Stefan Roese13b4f632012-08-14 15:04:19 +0200303/* Diagnosis Interface - see ticket #63 */
304#define CONFIG_SYS_CS4_START 0xEA000000
305#define CONFIG_SYS_CS4_SIZE 0x00000001
306/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
307#define CONFIG_SYS_CS4_CFG 0x0002B900
Stefan Roesed4451d32013-02-07 02:10:11 +0000308#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200309
Stefan Roesed4451d32013-02-07 02:10:11 +0000310/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200311#define CONFIG_SYS_CS5_START 0xE8000000
Stefan Roesed4451d32013-02-07 02:10:11 +0000312#ifdef CONFIG_A4M2K
313#define CONFIG_SYS_CS5_SIZE 0x00100000
314#else
Stefan Roese13b4f632012-08-14 15:04:19 +0200315#define CONFIG_SYS_CS5_SIZE 0x00010000
Stefan Roesed4451d32013-02-07 02:10:11 +0000316#endif
Stefan Roese13b4f632012-08-14 15:04:19 +0200317/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
318#define CONFIG_SYS_CS5_CFG 0x0032B900
319
320#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
321#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
Stefan Roesed4451d32013-02-07 02:10:11 +0000322#define CONFIG_SYS_CS1_CFG 0x0008FD00
Stefan Roese13b4f632012-08-14 15:04:19 +0200323#define CONFIG_SYS_CS2_CFG 0x0006F90C
324#else /* for pci_clk = 33 MHz */
325#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
326#define CONFIG_SYS_CS1_CFG 0x0001FB00
327#define CONFIG_SYS_CS2_CFG 0x0002F90C
328#endif
329
330#define CONFIG_SYS_CS_BURST 0x00000000
331/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
332/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
333/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
334#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
335
336#define CONFIG_SYS_RESET_ADDRESS 0xff000000
337
338/*
339 * Environment Configuration
340 */
341
Stefan Roese8aa34492013-04-25 23:20:23 +0000342#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
Stefan Roese13b4f632012-08-14 15:04:19 +0200343#undef CONFIG_BOOTARGS
344#define CONFIG_ZERO_BOOTDELAY_CHECK
345
Stefan Roese8aa34492013-04-25 23:20:23 +0000346#define CONFIG_SYS_AUTOLOAD "n"
347
Stefan Roese13b4f632012-08-14 15:04:19 +0200348#define CONFIG_PREBOOT "echo;" \
349 "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
350 "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
351 "echo"
352
353#undef CONFIG_BOOTARGS
354
Stefan Roese8aa34492013-04-25 23:20:23 +0000355#define CONFIG_SYS_OS_BASE 0xfc200000
356#define CONFIG_SYS_FDT_BASE 0xfc1e0000
Stefan Roese13b4f632012-08-14 15:04:19 +0200357
Stefan Roese13b4f632012-08-14 15:04:19 +0200358#define CONFIG_EXTRA_ENV_SETTINGS \
359 "netdev=eth0\0" \
360 "verify=no\0" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000361 "loadaddr=200000\0" \
362 "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
363 "kernel_addr_r=1000000\0" \
364 "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
365 "fdt_addr_r=1800000\0" \
366 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
367 "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
368 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
369 "rootpath=/opt/eldk-5.2.1/powerpc/" \
370 "core-image-minimal-mtdutils-dropbear-generic\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200371 "consoledev=ttyPSC0\0" \
372 "nfsargs=setenv bootargs root=/dev/nfs rw " \
373 "nfsroot=${serverip}:${rootpath}\0" \
374 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200375 "mtdargs=setenv bootargs root=/dev/mtdblock8 " \
Stefan Roese8aa34492013-04-25 23:20:23 +0000376 "rootfstype=squashfs,jffs2\0" \
377 "addhost=setenv bootargs ${bootargs} " \
378 "hostname=${hostname}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200379 "addip=setenv bootargs ${bootargs} " \
380 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
381 ":${hostname}:${netdev}:off panic=1\0" \
382 "addtty=setenv bootargs ${bootargs} " \
383 "console=${consoledev},${baudrate}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200384 "flash_nfs=run nfsargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000385 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200386 "flash_mtd=run mtdargs addip addtty addmtd addhost;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000387 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200388 "flash_self=run ramargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000389 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
390 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
391 "tftp ${fdt_addr_r} ${fdtfile};" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200392 "run nfsargs addip addtty addmtd addhost;" \
Stefan Roesed4451d32013-02-07 02:10:11 +0000393 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
394 "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
395 "/u-boot-img.bin\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200396 "update=protect off fc000000 fc07ffff;" \
Stefan Roese8aa34492013-04-25 23:20:23 +0000397 "era fc000000 fc07ffff;" \
398 "cp.b ${loadaddr} fc000000 ${filesize}\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200399 "upd=run load;run update\0" \
Stefan Roesed62a89b2013-06-22 16:16:25 +0200400 "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \
401 "run mtdargs addip addtty addmtd addhost;" \
402 "fdt addr 1800000;fdt boardsetup;fdt chosen;" \
403 "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \
404 "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \
405 "erase fc200000 fc6fffff;" \
406 "cp.b 1000000 fc200000 ${filesize}" \
407 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
408 "mtdids=" MTDIDS_DEFAULT "\0" \
409 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Stefan Roese13b4f632012-08-14 15:04:19 +0200410 ""
411
412#define CONFIG_BOOTCOMMAND "run flash_mtd"
413
414/*
415 * SPL related defines
416 */
Stefan Roese13b4f632012-08-14 15:04:19 +0200417#define CONFIG_SPL_FRAMEWORK
Stefan Roesed4451d32013-02-07 02:10:11 +0000418#define CONFIG_SPL_BOARD_INIT
Stefan Roese13b4f632012-08-14 15:04:19 +0200419#define CONFIG_SPL_NOR_SUPPORT
420#define CONFIG_SPL_TEXT_BASE 0xfc000000
421#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
422#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
423#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
424#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
425#define CONFIG_SPL_SERIAL_SUPPORT
426
427/* Place BSS for SPL near end of SDRAM */
428#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
429#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
430
431#define CONFIG_SPL_OS_BOOT
Ying Zhangba1bee42013-05-20 14:07:25 +0800432#define CONFIG_SPL_ENV_SUPPORT
Stefan Roese13b4f632012-08-14 15:04:19 +0200433/* Place patched DT blob (fdt) at this address */
434#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
435
436/* Settings for real U-Boot to be loaded from NOR flash */
437#ifndef __ASSEMBLY__
438extern char __spl_flash_end[];
439#endif
440#define CONFIG_SYS_UBOOT_BASE __spl_flash_end
441#define CONFIG_SYS_SPL_MAX_LEN (32 << 10)
442#define CONFIG_SYS_UBOOT_START 0x1000100
443
444#endif /* __CONFIG_H */