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Masahiro Yamada509eb672014-11-26 18:33:59 +09001/*
2 * Device Tree Source for UniPhier PH1-LD4 SoC
3 *
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +09004 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada509eb672014-11-26 18:33:59 +09005 *
Masahiro Yamada13b2ba12015-06-30 18:27:01 +09006 * SPDX-License-Identifier: GPL-2.0+ X11
Masahiro Yamada509eb672014-11-26 18:33:59 +09007 */
8
Masahiro Yamada8f062432015-12-16 10:54:07 +09009/include/ "uniphier-common32.dtsi"
Masahiro Yamada509eb672014-11-26 18:33:59 +090010
11/ {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090012 compatible = "socionext,ph1-ld4";
Masahiro Yamada509eb672014-11-26 18:33:59 +090013
14 cpus {
Masahiro Yamada509eb672014-11-26 18:33:59 +090015 #address-cells = <1>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +090016 #size-cells = <0>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090017
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a9";
21 reg = <0>;
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090022 next-level-cache = <&l2>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090023 };
24 };
25
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090026 clocks {
27 arm_timer_clk: arm_timer_clk {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <50000000>;
31 };
Masahiro Yamadad243c182015-08-28 22:33:13 +090032
33 uart_clk: uart_clk {
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <36864000>;
37 };
38
39 iobus_clk: iobus_clk {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <100000000>;
43 };
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090044 };
Masahiro Yamada8f062432015-12-16 10:54:07 +090045};
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090046
Masahiro Yamada8f062432015-12-16 10:54:07 +090047&soc {
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090048 l2: l2-cache@500c0000 {
49 compatible = "socionext,uniphier-system-cache";
50 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
51 interrupts = <0 174 4>, <0 175 4>;
52 cache-unified;
53 cache-size = <(512 * 1024)>;
54 cache-sets = <256>;
55 cache-line-size = <128>;
56 cache-level = <2>;
57 };
58
Masahiro Yamada8f062432015-12-16 10:54:07 +090059 i2c0: i2c@58400000 {
60 compatible = "socionext,uniphier-i2c";
61 status = "disabled";
62 reg = <0x58400000 0x40>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090063 #address-cells = <1>;
Masahiro Yamada8f062432015-12-16 10:54:07 +090064 #size-cells = <0>;
65 interrupts = <0 41 1>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_i2c0>;
68 clocks = <&iobus_clk>;
69 clock-frequency = <100000>;
70 };
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090071
Masahiro Yamada8f062432015-12-16 10:54:07 +090072 i2c1: i2c@58480000 {
73 compatible = "socionext,uniphier-i2c";
74 status = "disabled";
75 reg = <0x58480000 0x40>;
76 #address-cells = <1>;
77 #size-cells = <0>;
78 interrupts = <0 42 1>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_i2c1>;
81 clocks = <&iobus_clk>;
82 clock-frequency = <100000>;
83 };
Masahiro Yamada625177d2014-11-26 18:34:00 +090084
Masahiro Yamada8f062432015-12-16 10:54:07 +090085 /* chip-internal connection for DMD */
86 i2c2: i2c@58500000 {
87 compatible = "socionext,uniphier-i2c";
88 reg = <0x58500000 0x40>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 interrupts = <0 43 1>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c2>;
94 clocks = <&iobus_clk>;
95 clock-frequency = <400000>;
96 };
Masahiro Yamada625177d2014-11-26 18:34:00 +090097
Masahiro Yamada8f062432015-12-16 10:54:07 +090098 i2c3: i2c@58580000 {
99 compatible = "socionext,uniphier-i2c";
100 status = "disabled";
101 reg = <0x58580000 0x40>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 interrupts = <0 44 1>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c3>;
107 clocks = <&iobus_clk>;
108 clock-frequency = <100000>;
109 };
Masahiro Yamada625177d2014-11-26 18:34:00 +0900110
Masahiro Yamada8f062432015-12-16 10:54:07 +0900111 usb0: usb@5a800100 {
112 compatible = "socionext,uniphier-ehci", "generic-ehci";
113 status = "disabled";
114 reg = <0x5a800100 0x100>;
115 interrupts = <0 80 4>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_usb0>;
118 };
Masahiro Yamada625177d2014-11-26 18:34:00 +0900119
Masahiro Yamada8f062432015-12-16 10:54:07 +0900120 usb1: usb@5a810100 {
121 compatible = "socionext,uniphier-ehci", "generic-ehci";
122 status = "disabled";
123 reg = <0x5a810100 0x100>;
124 interrupts = <0 81 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_usb1>;
127 };
Masahiro Yamada149c7512014-11-26 18:34:01 +0900128
Masahiro Yamada8f062432015-12-16 10:54:07 +0900129 usb2: usb@5a820100 {
130 compatible = "socionext,uniphier-ehci", "generic-ehci";
131 status = "disabled";
132 reg = <0x5a820100 0x100>;
133 interrupts = <0 82 4>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_usb2>;
Masahiro Yamada509eb672014-11-26 18:33:59 +0900136 };
137};
Masahiro Yamadad243c182015-08-28 22:33:13 +0900138
Masahiro Yamada8f062432015-12-16 10:54:07 +0900139&serial0 {
140 clock-frequency = <36864000>;
141};
142
143&serial1 {
144 clock-frequency = <36864000>;
145};
146
147&serial2 {
148 clock-frequency = <36864000>;
149};
150
151&serial3 {
152 interrupts = <0 29 4>;
153 clock-frequency = <36864000>;
154};
155
156&pinctrl {
157 compatible = "socionext,ph1-ld4-pinctrl", "syscon";
158};