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Tom Rini83d290c2018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Stefanbfacf462011-12-23 06:35:04 +00002#
3# Copyright (C) 2011
Stefan Herbrechtsmeier16437a12014-12-28 14:09:50 +01004# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Stefanbfacf462011-12-23 06:35:04 +00005#
6# Based on Kirkwood support:
7# (C) Copyright 2009
8# Marvell Semiconductor <www.marvell.com>
9# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Anatolij Gustschinb1e6c4c2013-04-30 11:15:33 +000010# Refer doc/README.kwbimage for more details about how-to configure
Stefanbfacf462011-12-23 06:35:04 +000011# and create kirkwood boot image
12#
13
14# Boot Media configurations
15BOOT_FROM nand
16NAND_ECC_MODE default
17NAND_PAGE_SIZE 0x0800
18
19# SOC registers configuration using bootrom header extension
20# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
21
22# Configure RGMII-0 interface pad voltage to 1.8V
23DATA 0xFFD100e0 0x1b1b1b9b
24
25#Dram initalization for SINGLE x16 CL=5 @ 400MHz
26DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27# bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28# bit23-14: 0 required
29# bit24: 1, enable exit self refresh mode on DDR access
30# bit25: 1 required
31# bit29-26: 0 required
32# bit31-30: 0b01 required
33
34DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
35# bit3-0: 0 required
36# bit4: 0, addr/cmd in smame cycle
37# bit5: 0, clk is driven during self refresh, we don't care for APX
38# bit6: 0, use recommended falling edge of clk for addr/cmd
39# bit11-7: 0 required
40# bit12: 1 required
41# bit13: 1 required
42# bit14: 0, input buffer always powered up
43# bit17-15: 0 required
44# bit18: 1, cpu lock transaction enabled
45# bit19: 0 required
46# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
47# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
48# bit30-28: 3 required
49# bit31: 0, no additional STARTBURST delay
50
51DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
52# bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
53# bit7-4: 5, 6 cycle tRCD
54# bit11-8: 4, 5 cyle tRP
55# bit15-12: 5, 6 cyle tWR
56# bit19-16: 2, 3 cyle tWTR
57# bit20: 1, 18 cycle tRAS (tRAS[4])
58# bit23-21: 0 required
59# bit27-24: 2, 3 cycle tRRD
60# bit31-28: 2, 3 cyle tRTP
61
62DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
63# bit6-0: 0x33, 33 cycle tRFC
64# bit8-7: 0, 1 cycle tR2R
65# bit10-9: 0, 1 cyle tR2W
66# bit12-11: 1, 2 cylce tW2W
67# bit31-13: 0 required
68
69DATA 0xFFD01410 0x0000000c # DDR Address Control
70# bit1-0: 0, Cs0width=x8
71# bit3-2: 3, Cs0size=1Gb
72# bit5-4: 0, Cs1width=nonexistent
73# bit7-6: 0, Cs1size=nonexistent
74# bit9-8: 0, Cs2width=nonexistent
75# bit11-10: 0, Cs2size=nonexistent
76# bit13-12: 0, Cs3width=nonexistent
77# bit15-14: 0, Cs3size=nonexistent
78# bit16: 0, Cs0AddrSel
79# bit17: 0, Cs1AddrSel
80# bit18: 0, Cs2AddrSel
81# bit19: 0, Cs3AddrSel
82# bit31-20: 0 required
83
84DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
85# bit0: 0, OPEn=OpenPage enabled
86# bit31-1: 0 required
87
88DATA 0xFFD01418 0x00000000 # DDR Operation
89# bit3-0: 0, Cmd=Normal SDRAM Mode
90# bit31-4: 0 required
91
92DATA 0xFFD0141C 0x00000C52 # DDR Mode
93# bit2-0: 2, Burst Length (2 required)
94# bit3: 0, Burst Type (0 required)
95# bit6-4: 5, CAS Latency (CL) 5
96# bit7: 0, (Test Mode) Normal operation
97# bit8: 0, (Reset DLL) Normal operation
98# bit11-9: 0, Write recovery for auto-precharge (3 required ??)
99# bit12: 0, Fast Active power down exit time (0 required)
100# bit31-13: 0 required
101
102DATA 0xFFD01420 0x00000040 # DDR Extended Mode
103# bit0: 0, DRAM DLL enabled
104# bit1: 0, DRAM drive strength normal
105# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
106# bit5-3: 0 required
107# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
108# bit9-7: 0 required
109# bit10: 0, differential DQS enabled
110# bit11: 0 required
111# bit12: 0, DRAM output buffer enabled
112# bit31-13: 0 required
113
114DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
115# bit2-0: 0x7 required
116# bit3: 1, MBUS Burst Chop disabled
117# bit6-4: 0x7 required
118# bit7: 0 required
119# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
120# bit9: 0, no half clock cycle addition to dataout
121# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
122# bit11: 0, 1/4 clock cycle skew disabled for write mesh
123# bit15-12: 0xf required
124# bit31-16: 0 required
125
126DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
127# bit3-0: 0 required
128# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
129# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
130# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
132# bit31-20: 0 required
133
134DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
135# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
136# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
137# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
139# bit31-16: 0 required
140
141DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
142DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
143# bit0: 1, Window enabled
144# bit1: 0, Write Protect disabled
145# bit3-2: 0x0, CS0 hit selected
146# bit23-4: 0xfffff required
147# bit31-24: 0x0f, Size (i.e. 256MB)
148
149DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
150DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
151# bit0: 1, Window enabled
152# bit1: 0, Write Protect disabled
153# bit3-2: 1, CS1 hit selected
154# bit23-4: 0xfffff required
155# bit31-24: 0x0f, Size (i.e. 256MB)
156
157DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
158DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
159
160DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
161# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
162# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
163# bit15-8: 0 required
164# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
165# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
166# bit31-24: 0 required
167
168DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
169# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
170# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
171# bit31-4 0 required
172
173DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
174# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
175# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
176# bit9-8: 0, Internal ODT assertion is controlled by fiels
177# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
178# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
179# bit14: 1, M_STARTBURST_IN ODT enabled
180# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
181# bit20-16: 0, Pad N channel driving strength for ODT
182# bit25-21: 0, Pad P channel driving strength for ODT
183# bit31-26: 0 required
184
185DATA 0xFFD01480 0x00000001 # DDR Initialization Control
186# bit0: 1, enable DDR init upon this register write
187# bit31-1: 0, required
188
189# End of Header extension
190DATA 0x0 0x0