blob: 8680eb6ef5fd8c3b714fa41ab24b233f8b827504 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +09002/*
3 * Configuation settings for the Renesas Solutions AP-325RXA board
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +09007 */
8
9#ifndef __AP325RXA_H
10#define __AP325RXA_H
11
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090012#define CONFIG_CPU_SH7723 1
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090013
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020014#define CONFIG_DISPLAY_BOARDINFO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090015#undef CONFIG_SHOW_BOOT_PROGRESS
16
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090017/* MEMORY */
18#define AP325RXA_SDRAM_BASE (0x88000000)
19#define AP325RXA_FLASH_BASE_1 (0xA0000000)
20#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
21
22/* undef to save memory */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090023/* Monitor Command Prompt */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090024/* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090026/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090028
29/* SCIF */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090030#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
31#define CONFIG_CONS_SCIF5 1
32
33/* Suppress display of console information at boot */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090034
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
36#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090037
38/* Enable alternate, more extensive, memory test */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090039/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#undef CONFIG_SYS_MEMTEST_SCRATCH
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090041
42/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090044
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090046/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090048/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090050
51/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090053/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090055/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090058
59/* FLASH */
60#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_FLASH_CFI
62#undef CONFIG_SYS_FLASH_QUIET_TEST
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090063/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_FLASH_EMPTY_INFO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090065/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090067/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090069
70/*
71 * IDE support
72 */
73#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_PIO_MODE 1
75#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
76#define CONFIG_SYS_IDE_MAXDEVICE 1
77#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
78#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
79#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
80#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
81#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +053082#define CONFIG_IDE_SWAP_IO
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090083
84/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_MAX_FLASH_BANKS 1
86#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090087
88/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090090/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090092/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090094/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +090096
97/*
98 * Use hardware flash sectors protection instead
99 * of U-Boot software protection
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#undef CONFIG_SYS_FLASH_PROTECTION
102#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900103
104/* ENV setting */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900105#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200106#define CONFIG_ENV_SECT_SIZE (128 * 1024)
107#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
109/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
110#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200111#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900112
113/* Board Clock */
114#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900115#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
116#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200117#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu6f0da492008-08-22 17:39:09 +0900118
119#endif /* __AP325RXA_H */