blob: eddb201d4affb2c6f4ff2caf9723ebf34efcca8c [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Stephen Warren10a03382016-05-12 13:32:56 -06002/*
3 * Copyright (c) 2013-2016, NVIDIA CORPORATION.
Stephen Warren10a03382016-05-12 13:32:56 -06004 */
5
6#ifndef _P2771_0000_H
7#define _P2771_0000_H
8
9#include <linux/sizes.h>
10
11#include "tegra186-common.h"
12
13/* High-level configuration options */
14#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
15
Bryan Wuad3c1442016-07-27 15:48:22 -060016/* I2C */
17#define CONFIG_SYS_I2C_TEGRA
18
Stephen Warren10a03382016-05-12 13:32:56 -060019/* Environment in eMMC, at the end of 2nd "boot sector" */
Stephen Warren10a03382016-05-12 13:32:56 -060020#define CONFIG_SYS_MMC_ENV_DEV 0
21#define CONFIG_SYS_MMC_ENV_PART 2
22#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
23
Stephen Warrena6bb0082016-07-29 13:15:06 -060024/* PCI host support */
Stephen Warrena6bb0082016-07-29 13:15:06 -060025
Stephen Warrene43effc2018-01-08 17:41:25 -070026#define BOARD_EXTRA_ENV_SETTINGS \
27 "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
28 "ramdisk_addr_r\0" \
29 "kernel_addr_r_align=00200000\0" \
30 "kernel_addr_r_offset=00080000\0" \
31 "kernel_addr_r_size=02000000\0" \
32 "kernel_addr_r_aliases=loadaddr\0" \
33 "fdt_addr_r_align=00200000\0" \
34 "fdt_addr_r_offset=00000000\0" \
35 "fdt_addr_r_size=00200000\0" \
36 "scriptaddr_align=00200000\0" \
37 "scriptaddr_offset=00000000\0" \
38 "scriptaddr_size=00200000\0" \
39 "pxefile_addr_r_align=00200000\0" \
40 "pxefile_addr_r_offset=00000000\0" \
41 "pxefile_addr_r_size=00200000\0" \
42 "ramdisk_addr_r_align=00200000\0" \
43 "ramdisk_addr_r_offset=00000000\0" \
44 "ramdisk_addr_r_size=02000000\0"
45
Stephen Warren10a03382016-05-12 13:32:56 -060046#include "tegra-common-post.h"
47
48/* Crystal is 38.4MHz. clk_m runs at half that rate */
49#define COUNTER_FREQUENCY 19200000
50
Stephen Warrena9819b92018-01-03 14:32:35 -070051#undef CONFIG_NR_DRAM_BANKS
52#define CONFIG_NR_DRAM_BANKS (1024 + 2)
53
Stephen Warren10a03382016-05-12 13:32:56 -060054#endif