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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glassc861fbf2011-10-03 19:26:47 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glassc861fbf2011-10-03 19:26:47 +00004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Simon Glasse2ee1002013-06-11 11:14:44 -07009#ifdef FTRACE
10#define CONFIG_TRACE
Simon Glasse2ee1002013-06-11 11:14:44 -070011#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
12#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
13#define CONFIG_TRACE_EARLY
14#define CONFIG_TRACE_EARLY_ADDR 0x00100000
15
16#endif
17
Simon Glass1c12bce2016-07-04 11:57:52 -060018#ifndef CONFIG_SPL_BUILD
Simon Glass42d3b292014-06-11 23:29:43 -060019#define CONFIG_IO_TRACE
Simon Glass1c12bce2016-07-04 11:57:52 -060020#endif
Simon Glass42d3b292014-06-11 23:29:43 -060021
Thomas Chou9961a0b2015-10-30 15:35:52 +080022#ifndef CONFIG_TIMER
Rob Herring28c860b2013-11-08 08:40:44 -060023#define CONFIG_SYS_TIMER_RATE 1000000
Thomas Chou9961a0b2015-10-30 15:35:52 +080024#endif
Rob Herring28c860b2013-11-08 08:40:44 -060025
Simon Glass7b06b662012-02-15 15:51:12 -080026#define CONFIG_LMB
27
Henrik Nordströmf4d8de42013-11-10 10:26:56 -070028#define CONFIG_HOST_MAX_DEVICES 4
Simon Glass10fc1212012-12-26 09:53:37 +000029
Simon Glassc861fbf2011-10-03 19:26:47 +000030/*
Simon Glassb53e94b2014-07-10 22:23:32 -060031 * Size of malloc() pool, before and after relocation
Simon Glassc861fbf2011-10-03 19:26:47 +000032 */
Simon Glassb53e94b2014-07-10 22:23:32 -060033#define CONFIG_MALLOC_F_ADDR 0x0010000
Simon Glass9f604422014-02-27 13:25:56 -070034#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
Simon Glassc861fbf2011-10-03 19:26:47 +000035
Simon Glassc861fbf2011-10-03 19:26:47 +000036#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
37
Simon Glassc861fbf2011-10-03 19:26:47 +000038/* turn on command-line edit/c/auto */
Simon Glassc861fbf2011-10-03 19:26:47 +000039
40#define CONFIG_ENV_SIZE 8192
Simon Glassc861fbf2011-10-03 19:26:47 +000041
Simon Glass5e749342014-09-15 06:33:20 -060042/* SPI - enable all SPI flash types for testing purposes */
Mike Frysingerca9a5012013-12-03 16:43:28 -070043
Simon Glassac395f02014-12-10 08:55:52 -070044#define CONFIG_I2C_EDID
Simon Glassac395f02014-12-10 08:55:52 -070045
Simon Glassc861fbf2011-10-03 19:26:47 +000046/* Memory things - we don't really want a memory test */
Simon Glassecdbf412013-02-24 20:29:23 +000047#define CONFIG_SYS_LOAD_ADDR 0x00000000
48#define CONFIG_SYS_MEMTEST_START 0x00100000
Simon Glassc861fbf2011-10-03 19:26:47 +000049#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
Simon Glass2c072c92014-02-27 13:26:25 -070050#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
51
52#define CONFIG_PHYSMEM
Simon Glassc861fbf2011-10-03 19:26:47 +000053
54/* Size of our emulated memory */
Simon Glassa733b062013-04-26 02:53:43 +000055#define CONFIG_SYS_SDRAM_BASE 0
Simon Glassc861fbf2011-10-03 19:26:47 +000056#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
Simon Glassa733b062013-04-26 02:53:43 +000057#define CONFIG_SYS_MONITOR_BASE 0
58#define CONFIG_NR_DRAM_BANKS 1
Simon Glassc861fbf2011-10-03 19:26:47 +000059
Simon Glassc861fbf2011-10-03 19:26:47 +000060#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
61 115200}
Simon Glassc861fbf2011-10-03 19:26:47 +000062
Sjoerd Simons791a9f62015-04-13 22:54:27 +020063#define BOOT_TARGET_DEVICES(func) \
64 func(HOST, host, 1) \
65 func(HOST, host, 0)
66
67#include <config_distro_bootcmd.h>
Simon Glassc861fbf2011-10-03 19:26:47 +000068
Joe Hershberger1f5bc522015-04-08 01:41:25 -050069#define CONFIG_KEEP_SERVERADDR
70#define CONFIG_UDP_CHECKSUM
Joe Hershberger1f5bc522015-04-08 01:41:25 -050071#define CONFIG_TIMESTAMP
Joe Hershbergerf3e0c372015-03-22 17:09:22 -050072#define CONFIG_BOOTP_DNS2
Joe Hershbergerf3e0c372015-03-22 17:09:22 -050073#define CONFIG_BOOTP_SEND_HOSTNAME
74#define CONFIG_BOOTP_SERVERIP
Joe Hershbergerf3e0c372015-03-22 17:09:22 -050075#define CONFIG_IP_DEFRAG
Simon Glassc861fbf2011-10-03 19:26:47 +000076
Simon Glassad0e4632014-03-22 17:12:58 -060077#ifndef SANDBOX_NO_SDL
Simon Glass2c072c92014-02-27 13:26:25 -070078#define CONFIG_SANDBOX_SDL
Simon Glassad0e4632014-03-22 17:12:58 -060079#endif
80
81/* LCD and keyboard require SDL support */
82#ifdef CONFIG_SANDBOX_SDL
Simon Glass2c072c92014-02-27 13:26:25 -070083#define LCD_BPP LCD_COLOR16
Simon Glass01564442014-10-15 04:53:04 -060084#define CONFIG_LCD_BMP_RLE8
Simon Glass747440d2016-01-18 19:52:28 -070085#define CONFIG_VIDEO_BMP_RLE8
86#define CONFIG_SPLASH_SCREEN_ALIGN
Simon Glass2c072c92014-02-27 13:26:25 -070087
Simon Glassad0e4632014-03-22 17:12:58 -060088#define CONFIG_KEYBOARD
89
Simon Glass460a7172015-11-08 23:48:07 -070090#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
Simon Glassf1a12472016-01-21 19:44:51 -070091 "stdout=serial,vidconsole\0" \
92 "stderr=serial,vidconsole\0"
Simon Glassad0e4632014-03-22 17:12:58 -060093#else
Joe Hershberger3ea143a2015-03-22 17:09:13 -050094#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
Simon Glassf1a12472016-01-21 19:44:51 -070095 "stdout=serial,vidconsole\0" \
96 "stderr=serial,vidconsole\0"
Simon Glassad0e4632014-03-22 17:12:58 -060097#endif
Simon Glassc861fbf2011-10-03 19:26:47 +000098
Joe Hershberger3ea143a2015-03-22 17:09:13 -050099#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
100 "eth1addr=00:00:11:22:33:45\0" \
Bin Meng71d79712015-08-27 22:25:53 -0700101 "eth3addr=00:00:11:22:33:46\0" \
102 "eth5addr=00:00:11:22:33:47\0" \
Joe Hershberger3ea143a2015-03-22 17:09:13 -0500103 "ipaddr=1.2.3.4\0"
104
Sjoerd Simons791a9f62015-04-13 22:54:27 +0200105#define MEM_LAYOUT_ENV_SETTINGS \
106 "bootm_size=0x10000000\0" \
107 "kernel_addr_r=0x1000000\0" \
108 "fdt_addr_r=0xc00000\0" \
109 "ramdisk_addr_r=0x2000000\0" \
110 "scriptaddr=0x1000\0" \
111 "pxefile_addr_r=0x2000\0"
112
113#define CONFIG_EXTRA_ENV_SETTINGS \
114 SANDBOX_SERIAL_SETTINGS \
115 SANDBOX_ETH_SETTINGS \
116 BOOTENV \
117 MEM_LAYOUT_ENV_SETTINGS
Joe Hershberger3ea143a2015-03-22 17:09:13 -0500118
Kees Cook3153e912013-08-16 07:59:11 -0700119#define CONFIG_GZIP_COMPRESSED
120#define CONFIG_BZIP2
Kees Cook3153e912013-08-16 07:59:11 -0700121
Simon Glass1c12bce2016-07-04 11:57:52 -0600122#ifndef CONFIG_SPL_BUILD
Simon Glass74c6dc12016-05-01 11:36:23 -0600123#define CONFIG_SYS_IDE_MAXBUS 1
124#define CONFIG_SYS_ATA_IDE0_OFFSET 0
125#define CONFIG_SYS_IDE_MAXDEVICE 2
126#define CONFIG_SYS_ATA_BASE_ADDR 0x100
127#define CONFIG_SYS_ATA_DATA_OFFSET 0
128#define CONFIG_SYS_ATA_REG_OFFSET 1
129#define CONFIG_SYS_ATA_ALT_OFFSET 2
130#define CONFIG_SYS_ATA_STRIDE 4
Simon Glass1c12bce2016-07-04 11:57:52 -0600131#endif
Simon Glass74c6dc12016-05-01 11:36:23 -0600132
Simon Glasse8c0a252016-05-01 11:36:25 -0600133#define CONFIG_SCSI_AHCI_PLAT
134#define CONFIG_SYS_SCSI_MAX_DEVICE 2
135#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
136#define CONFIG_SYS_SCSI_MAX_LUN 4
137
Simon Glass199a1202016-05-01 11:36:27 -0600138#define CONFIG_SYS_SATA_MAX_DEVICE 2
139
Simon Glass68969772017-03-28 10:27:28 -0600140#define CONFIG_MISC_INIT_F
141
Simon Glassc861fbf2011-10-03 19:26:47 +0000142#endif