blob: 85dea400c8fc1e4c8b85f6bcd2886cba21f4f720 [file] [log] [blame]
Shinya Kuribayashi4a1f11b2008-04-22 22:47:27 +09001
2Notes for the MIPS architecture port of U-Boot
3
4Toolchains
5----------
6
7 http://www.denx.de/wiki/DULG/ELDK
8 ELDK < DULG < DENX
9
10 http://www.emdebian.org/crosstools.html
11 Embedded Debian -- Cross-development toolchains
12
13 http://buildroot.uclibc.org/
14 Buildroot
15
16Known Issues
17------------
18
19 * Little endian build problem
20
21 If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all
22 objects will be generated in big-endian format.
23
24 * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
25
26 Cache will be disabled before entering the loaded ELF image without
27 writing back and invalidating cache lines. This leads to cache
28 incoherency in most cases, unless the code gets loaded after U-Boot
29 re-initializes the cache. The more common uImage 'bootm' command does
30 not suffer this problem.
31
32 [workaround] To avoid this cache incoherency,
33 1) insert flush_cache(all) before calling dcache_disable(), or
34 2) fix dcache_disable() to do both flushing and disabling cache.
35
36 * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
37 or override do_bootelf_exec() not to disable I-/D-caches, because most
38 Linux/MIPS ports don't re-enable caches after entering kernel_entry.
39
40TODOs
41-----
42
43 * Probe CPU types, I-/D-cache and TLB size etc. automatically
44
45 * Secondary cache support missing
46
47 * Centralize the link directive files
48
49 * Initialize TLB entries redardless of their use
50
51 * R2000/R3000 class parts are not supported
52
53 * Limited testing across different MIPS variants
54
55 * Due to cache initialization issues, the DRAM on board must be
56 initialized in board specific assembler language before the cache init
57 code is run -- that is, initialize the DRAM in lowlevel_init().