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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * Change log:
25 *
26 * 20050101: Eran Liberty (liberty@freescale.com)
27 * Initial file creating (porting from 85XX & 8260)
28 */
29
30/*
31 * PCI Configuration space access support for MPC85xx PCI Bridge
32 */
33#include <asm/mmu.h>
34#include <asm/io.h>
35#include <common.h>
36#include <pci.h>
37
Marian Balakowicze6f2e902005-10-11 19:09:42 +020038#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
Eran Libertyf046ccd2005-07-28 10:08:46 -050039#include <asm/i2c.h>
40#endif
41
42#if defined(CONFIG_PCI)
43
44void
45pci_mpc83xx_init(volatile struct pci_controller *hose)
46{
47 volatile immap_t * immr;
Jon Loeligerde1d0a62005-08-01 13:20:47 -050048 volatile clk8349_t * clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -050049 volatile law8349_t * pci_law;
50 volatile pot8349_t * pci_pot;
51 volatile pcictrl8349_t * pci_ctrl;
52 volatile pciconf8349_t * pci_conf;
Jon Loeligerde1d0a62005-08-01 13:20:47 -050053
Eran Libertyf046ccd2005-07-28 10:08:46 -050054 u8 val8,tmp8,ret;
55 u16 reg16,tmp16;
56 u32 val32,tmp32;
57
58 immr = (immap_t *)CFG_IMMRBAR;
59 clk = (clk8349_t *)&immr->clk;
60 pci_law = immr->sysconf.pcilaw;
61 pci_pot = immr->ios.pot;
62 pci_ctrl = immr->pci_ctrl;
63 pci_conf = immr->pci_conf;
64
65 /*
66 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
67 */
68 val32 = clk->occr;
69 udelay(2000);
70 clk->occr = 0xff000000;
71 udelay(2000);
Jon Loeligerde1d0a62005-08-01 13:20:47 -050072
Eran Libertyf046ccd2005-07-28 10:08:46 -050073 /*
74 * Configure PCI Local Access Windows
75 */
76 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
77 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
78 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
79 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
80
81 /*
82 * Configure PCI Outbound Translation Windows
83 */
84 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
85 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
86 pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
87
88 /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
89 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
90 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
91 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
Jon Loeligerde1d0a62005-08-01 13:20:47 -050092
Eran Libertyf046ccd2005-07-28 10:08:46 -050093 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
94 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
95 pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
96
97 /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
98 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
99 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
100 pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500101
Eran Libertyf046ccd2005-07-28 10:08:46 -0500102 /*
103 * Configure PCI Inbound Translation Windows
104 */
105 pci_ctrl[0].pitar1 = 0x0;
106 pci_ctrl[0].pibar1 = 0x0;
107 pci_ctrl[0].piebar1 = 0x0;
108 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
109
110 pci_ctrl[1].pitar1 = 0x0;
111 pci_ctrl[1].pibar1 = 0x0;
112 pci_ctrl[1].piebar1 = 0x0;
113 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
114 /*
115 * Assign PIB PMC slot to desired PCI bus
116 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200117#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500118 mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
119 i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
120#endif
121 val8 = 0;
122 ret = i2c_write(0x23,0x6,1,&val8,1);
123 ret = i2c_write(0x23,0x7,1,&val8,1);
124 val8 = 0xff;
125 ret = i2c_write(0x23,0x2,1,&val8,1);
126 ret = i2c_write(0x23,0x3,1,&val8,1);
127
128 val8 = 0;
129 ret = i2c_write(0x26,0x6,1,&val8,1);
130 val8 = 0x34;
131 ret = i2c_write(0x26,0x7,1,&val8,1);
132#if defined(PCI_64BIT)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500133 val8 = 0xf4; /* PMC2<->PCI1 64bit */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500134#elif defined(PCI_ALL_PCI1)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500135 val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500136#elif defined(PCI_ONE_PCI1)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500137 val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500138#elif defined(PCI_TWO_PCI1)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500139 val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500140#else
141 val8 = 0xf5;
142#endif
143 ret = i2c_write(0x26,0x2,1,&val8,1);
144 val8 = 0xff;
145 ret = i2c_write(0x26,0x3,1,&val8,1);
146 val8 = 0;
147 ret = i2c_write(0x27,0x6,1,&val8,1);
148 ret = i2c_write(0x27,0x7,1,&val8,1);
149 val8 = 0xff;
150 ret = i2c_write(0x27,0x2,1,&val8,1);
151 val8 = 0xef;
152 ret = i2c_write(0x27,0x3,1,&val8,1);
153 asm("eieio");
154
155 /*
156 * Release PCI RST Output signal
157 */
158 udelay(2000);
159 pci_ctrl[0].gcr = 1;
160#ifndef PCI_64BIT
161 pci_ctrl[1].gcr = 1;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500162#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500163 udelay(2000);
164
165 hose[0].first_busno = 0;
166 hose[0].last_busno = 0xff;
167
168 pci_set_region(hose[0].regions + 0,
169 CFG_PCI1_MEM_BASE,
170 CFG_PCI1_MEM_PHYS,
171 CFG_PCI1_MEM_SIZE,
172 PCI_REGION_MEM);
173
174 pci_set_region(hose[0].regions + 1,
175 CFG_PCI1_IO_BASE,
176 CFG_PCI1_IO_PHYS,
177 CFG_PCI1_IO_SIZE,
178 PCI_REGION_IO);
179
180 hose[0].region_count = 2;
181
182 pci_setup_indirect(&hose[0],
183 (CFG_IMMRBAR+0x8300),
184 (CFG_IMMRBAR+0x8304));
185#define PCI_CLASS_BRIDGE 0x06
186 reg16 = 0xff;
187 tmp32 = 0xffff;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500188 pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500189
190 pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
191 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
192 pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
193
194 /*
195 * Clear non-reserved bits in status register.
196 */
197 pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
198 pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
199#ifndef PCI_64BIT
200 hose[1].first_busno = 0;
201 hose[1].last_busno = 0xff;
202
203 pci_set_region(hose[1].regions + 0,
204 CFG_PCI2_MEM_BASE,
205 CFG_PCI2_MEM_PHYS,
206 CFG_PCI2_MEM_SIZE,
207 PCI_REGION_MEM);
208
209 pci_set_region(hose[1].regions + 1,
210 CFG_PCI2_IO_BASE,
211 CFG_PCI2_IO_PHYS,
212 CFG_PCI2_IO_SIZE,
213 PCI_REGION_IO);
214
215 hose[1].region_count = 2;
216
217 pci_setup_indirect(&hose[1],
218 (CFG_IMMRBAR+0x8380),
219 (CFG_IMMRBAR+0x8384));
220
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500221 pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500222 pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
223 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
224 pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
225
226 /*
227 * Clear non-reserved bits in status register.
228 */
229 pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
230 pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
231#endif
232
233#if defined(PCI_64BIT)
234 printf("PCI1 64bit on PMC2\n");
235#elif defined(PCI_ALL_PCI1)
236 printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
237#elif defined(PCI_ONE_PCI1)
238 printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
239#else
240 printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
241#endif
242
243#if 1
244 /*
245 * Hose scan.
246 */
247 pci_register_hose(hose);
248 hose->last_busno = pci_hose_scan(hose);
249#endif
250}
251
252#endif /* CONFIG_PCI */