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wdenk9dd41a72005-05-12 22:48:09 +00001/*
2 * (C) Copyright 2005
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37#define CONFIG_MPC8272_FAMILY 1
38#define CONFIG_IDS8247 1
39#define CPU_ID_STR "MPC8247"
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk9dd41a72005-05-12 22:48:09 +000041
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xfff00000
43
wdenk9dd41a72005-05-12 22:48:09 +000044#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45
46#define CONFIG_BOOTCOUNT_LIMIT
47
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010048#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk9dd41a72005-05-12 22:48:09 +000049
50#undef CONFIG_BOOTARGS
51
52#define CONFIG_EXTRA_ENV_SETTINGS \
53 "netdev=eth0\0" \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "nfsroot=${serverip}:${rootpath}\0" \
wdenk9dd41a72005-05-12 22:48:09 +000056 "ramargs=setenv bootargs root=/dev/ram rw " \
57 "console=ttyS0,115200\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058 "addip=setenv bootargs ${bootargs} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
60 ":${hostname}:${netdev}:off panic=1\0" \
wdenk9dd41a72005-05-12 22:48:09 +000061 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "bootm ${kernel_addr}\0" \
wdenk9dd41a72005-05-12 22:48:09 +000063 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010064 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
65 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk9dd41a72005-05-12 22:48:09 +000066 "rootpath=/opt/eldk/ppc_82xx\0" \
67 "bootfile=/tftpboot/IDS8247/uImage\0" \
68 "kernel_addr=ff800000\0" \
69 "ramdisk_addr=ffa00000\0" \
70 ""
71#define CONFIG_BOOTCOMMAND "run flash_self"
72
73#define CONFIG_MISC_INIT_R 1
74
75/* enable I2C and select the hardware/software driver */
76#undef CONFIG_HARD_I2C /* I2C with hardware support */
77#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
79#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk9dd41a72005-05-12 22:48:09 +000080
81/*
82 * Software (bit-bang) I2C driver configuration
83 */
84
85#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
86#define I2C_ACTIVE (iop->pdir |= 0x00000080)
87#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
88#define I2C_READ ((iop->pdat & 0x00000080) != 0)
89#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
90 else iop->pdat &= ~0x00000080
91#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
92 else iop->pdat &= ~0x00000100
93#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
94
95#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
97#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
98#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
99#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk9dd41a72005-05-12 22:48:09 +0000100
101#define CONFIG_I2C_X
102#endif
103
104/*
105 * select serial console configuration
106 * use the extern UART for the console
107 */
108#define CONFIG_CONS_INDEX 1
109#define CONFIG_BAUDRATE 115200
110/*
111 * NS16550 Configuration
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_NS16550
114#define CONFIG_SYS_NS16550_SERIAL
wdenk9dd41a72005-05-12 22:48:09 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk9dd41a72005-05-12 22:48:09 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_NS16550_CLK 14745600
wdenk9dd41a72005-05-12 22:48:09 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_UART_BASE 0xE0000000
121#define CONFIG_SYS_UART_SIZE 0x10000
wdenk9dd41a72005-05-12 22:48:09 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
wdenk9dd41a72005-05-12 22:48:09 +0000124
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200125
126/* pass open firmware flat tree */
127#define CONFIG_OF_LIBFDT 1
128#define CONFIG_OF_BOARD_SETUP 1
129
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200130#define OF_TBCLK (bd->bi_busfreq / 4)
131#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
132
133
wdenk9dd41a72005-05-12 22:48:09 +0000134/*
135 * select ethernet configuration
136 *
137 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
138 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
139 * for FCC)
140 *
141 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500142 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk9dd41a72005-05-12 22:48:09 +0000143 */
144#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
145#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
146#undef CONFIG_ETHER_NONE /* define if ether on something else */
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200147#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
148#define CONFIG_ETHER_ON_FCC1
149#define FCC_ENET
wdenk9dd41a72005-05-12 22:48:09 +0000150
151/*
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200152 * - Rx-CLK is CLK10
153 * - Tx-CLK is CLK9
wdenk9dd41a72005-05-12 22:48:09 +0000154 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
155 * - Enable Full Duplex in FSMR
156 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000157# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
158# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159# define CONFIG_SYS_CPMFCR_RAMTYPE 0
160# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk9dd41a72005-05-12 22:48:09 +0000161
162
163/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
164#define CONFIG_8260_CLKIN 66666666 /* in Hz */
165
166#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk9dd41a72005-05-12 22:48:09 +0000168
169#undef CONFIG_WATCHDOG /* watchdog disabled */
170
171#define CONFIG_TIMESTAMP /* Print image info with timestamp */
172
Jon Loeliger7be044e2007-07-09 21:24:19 -0500173/*
174 * BOOTP options
175 */
176#define CONFIG_BOOTP_SUBNETMASK
177#define CONFIG_BOOTP_GATEWAY
178#define CONFIG_BOOTP_HOSTNAME
179#define CONFIG_BOOTP_BOOTPATH
180#define CONFIG_BOOTP_BOOTFILESIZE
wdenk9dd41a72005-05-12 22:48:09 +0000181
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200182#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk9dd41a72005-05-12 22:48:09 +0000184
Jon Loeliger348f2582007-07-08 13:46:18 -0500185/*
186 * Command line configuration.
187 */
188#include <config_cmd_default.h>
189
190#define CONFIG_CMD_DHCP
191#define CONFIG_CMD_NFS
192#define CONFIG_CMD_NAND
193#define CONFIG_CMD_I2C
194#define CONFIG_CMD_SNTP
195
wdenk9dd41a72005-05-12 22:48:09 +0000196
197/*
198 * Miscellaneous configurable options
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_LONGHELP /* undef to save memory */
201#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500202#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk9dd41a72005-05-12 22:48:09 +0000204#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk9dd41a72005-05-12 22:48:09 +0000206#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
208#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
209#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk9dd41a72005-05-12 22:48:09 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
212#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk9dd41a72005-05-12 22:48:09 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk9dd41a72005-05-12 22:48:09 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk9dd41a72005-05-12 22:48:09 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk9dd41a72005-05-12 22:48:09 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
wdenk9dd41a72005-05-12 22:48:09 +0000221
222/*
223 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk9dd41a72005-05-12 22:48:09 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200230#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
Stefan Roeseca5def32010-08-31 10:00:10 +0200232#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk9dd41a72005-05-12 22:48:09 +0000233/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200234 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
wdenk9dd41a72005-05-12 22:48:09 +0000235 * The main FLASH is whichever is connected to *CS0.
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
238#define CONFIG_SYS_FLASH0_SIZE 8
wdenk9dd41a72005-05-12 22:48:09 +0000239
240/* Flash bank size (for preliminary settings)
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
wdenk9dd41a72005-05-12 22:48:09 +0000243
244/*-----------------------------------------------------------------------
245 * FLASH organization
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk9dd41a72005-05-12 22:48:09 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
250#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk9dd41a72005-05-12 22:48:09 +0000251
252/* Environment in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200253#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200255#define CONFIG_ENV_SIZE 0x20000
256#define CONFIG_ENV_SECT_SIZE 0x20000
wdenk9dd41a72005-05-12 22:48:09 +0000257
258/*-----------------------------------------------------------------------
259 * NAND-FLASH stuff
260 *-----------------------------------------------------------------------
261 */
Jon Loeliger348f2582007-07-08 13:46:18 -0500262#if defined(CONFIG_CMD_NAND)
wdenk9dd41a72005-05-12 22:48:09 +0000263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_NAND0_BASE 0xE1000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenk9dd41a72005-05-12 22:48:09 +0000266
Jon Loeliger11799432007-07-10 09:02:57 -0500267#endif /* CONFIG_CMD_NAND */
wdenk9dd41a72005-05-12 22:48:09 +0000268
269/*-----------------------------------------------------------------------
270 * Hard Reset Configuration Words
271 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk9dd41a72005-05-12 22:48:09 +0000273 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk9dd41a72005-05-12 22:48:09 +0000275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
wdenk9dd41a72005-05-12 22:48:09 +0000277
278/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_HRCW_SLAVE1 0
280#define CONFIG_SYS_HRCW_SLAVE2 0
281#define CONFIG_SYS_HRCW_SLAVE3 0
282#define CONFIG_SYS_HRCW_SLAVE4 0
283#define CONFIG_SYS_HRCW_SLAVE5 0
284#define CONFIG_SYS_HRCW_SLAVE6 0
285#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk9dd41a72005-05-12 22:48:09 +0000286
287/*-----------------------------------------------------------------------
288 * Internal Memory Mapped Register
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_IMMR 0xF0000000
wdenk9dd41a72005-05-12 22:48:09 +0000291
292/*-----------------------------------------------------------------------
293 * Definitions for initial stack pointer and data area (in DPRAM)
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200296#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200297#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk9dd41a72005-05-12 22:48:09 +0000299
300/*-----------------------------------------------------------------------
301 * Start addresses for the final memory configuration
302 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk9dd41a72005-05-12 22:48:09 +0000304 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
wdenk9dd41a72005-05-12 22:48:09 +0000306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_SDRAM_BASE 0x00000000
308#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200309#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
311#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk9dd41a72005-05-12 22:48:09 +0000312
wdenk9dd41a72005-05-12 22:48:09 +0000313/*-----------------------------------------------------------------------
314 * Cache Configuration
315 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger348f2582007-07-08 13:46:18 -0500317#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk9dd41a72005-05-12 22:48:09 +0000319#endif
320
321/*-----------------------------------------------------------------------
322 * HIDx - Hardware Implementation-dependent Registers 2-11
323 *-----------------------------------------------------------------------
324 * HID0 also contains cache control - initially enable both caches and
325 * invalidate contents, then the final state leaves only the instruction
326 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
327 * but Soft reset does not.
328 *
329 * HID1 has only read-only information - nothing to set.
330 */
331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
333#define CONFIG_SYS_HID0_FINAL 0
334#define CONFIG_SYS_HID2 0
wdenk9dd41a72005-05-12 22:48:09 +0000335
336/*-----------------------------------------------------------------------
337 * RMR - Reset Mode Register 5-5
338 *-----------------------------------------------------------------------
339 * turn on Checkstop Reset Enable
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_RMR 0
wdenk9dd41a72005-05-12 22:48:09 +0000342
343/*-----------------------------------------------------------------------
344 * BCR - Bus Configuration 4-25
345 *-----------------------------------------------------------------------
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_BCR 0
wdenk9dd41a72005-05-12 22:48:09 +0000348
349/*-----------------------------------------------------------------------
350 * SIUMCR - SIU Module Configuration 4-31
351 *-----------------------------------------------------------------------
352 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
wdenk9dd41a72005-05-12 22:48:09 +0000354
355/*-----------------------------------------------------------------------
356 * SYPCR - System Protection Control 4-35
357 * SYPCR can only be written once after reset!
358 *-----------------------------------------------------------------------
359 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
360 */
361#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk9dd41a72005-05-12 22:48:09 +0000363 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
364#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk9dd41a72005-05-12 22:48:09 +0000366 SYPCR_SWRI|SYPCR_SWP)
367#endif /* CONFIG_WATCHDOG */
368
369/*-----------------------------------------------------------------------
370 * TMCNTSC - Time Counter Status and Control 4-40
371 *-----------------------------------------------------------------------
372 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
373 * and enable Time Counter
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk9dd41a72005-05-12 22:48:09 +0000376
377/*-----------------------------------------------------------------------
378 * PISCR - Periodic Interrupt Status and Control 4-42
379 *-----------------------------------------------------------------------
380 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
381 * Periodic timer
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk9dd41a72005-05-12 22:48:09 +0000384
385/*-----------------------------------------------------------------------
386 * SCCR - System Clock Control 9-8
387 *-----------------------------------------------------------------------
388 * Ensure DFBRG is Divide by 16
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
wdenk9dd41a72005-05-12 22:48:09 +0000391
392/*-----------------------------------------------------------------------
393 * RCCR - RISC Controller Configuration 13-7
394 *-----------------------------------------------------------------------
395 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_RCCR 0
wdenk9dd41a72005-05-12 22:48:09 +0000397
398/*
399 * Init Memory Controller:
400 *
401 * Bank Bus Machine PortSz Device
402 * ---- --- ------- ------ ------
403 * 0 60x GPCM 16 bit FLASH
404 * 1 60x GPCM 8 bit NAND
405 * 2 60x SDRAM 32 bit SDRAM
406 * 3 60x GPCM 8 bit UART
407 *
408 */
409
410#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
411
412/* Minimum mask to separate preliminary
413 * address ranges for CS[0:2]
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
wdenk9dd41a72005-05-12 22:48:09 +0000416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_MPTPR 0x6600
wdenk9dd41a72005-05-12 22:48:09 +0000418
419/*-----------------------------------------------------------------------------
420 * Address for Mode Register Set (MRS) command
421 *-----------------------------------------------------------------------------
422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MRS_OFFS 0x00000110
wdenk9dd41a72005-05-12 22:48:09 +0000424
425
426/* Bank 0 - FLASH
427 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk9dd41a72005-05-12 22:48:09 +0000429 BRx_PS_8 |\
430 BRx_MS_GPCM_P |\
431 BRx_V)
432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk9dd41a72005-05-12 22:48:09 +0000434 ORxG_SCY_6_CLK )
435
Jon Loeliger348f2582007-07-08 13:46:18 -0500436#if defined(CONFIG_CMD_NAND)
wdenk9dd41a72005-05-12 22:48:09 +0000437/* Bank 1 - NAND Flash
438*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
440#define CONFIG_SYS_NAND_SIZE 0x8000
wdenk9dd41a72005-05-12 22:48:09 +0000441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_OR_TIMING_NAND 0x000036
wdenk9dd41a72005-05-12 22:48:09 +0000443
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
445#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
wdenk9dd41a72005-05-12 22:48:09 +0000446#endif
447
448/* Bank 2 - 60x bus SDRAM
449 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_PSRT 0x20
451#define CONFIG_SYS_LSRT 0x20
wdenk9dd41a72005-05-12 22:48:09 +0000452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenk9dd41a72005-05-12 22:48:09 +0000454 BRx_PS_32 |\
455 BRx_MS_SDRAM_P |\
456 BRx_V)
457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
wdenk9dd41a72005-05-12 22:48:09 +0000459
460
461/* SDRAM initialization values
462*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk9dd41a72005-05-12 22:48:09 +0000464 ORxS_BPD_4 |\
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200465 ORxS_ROWST_PBI0_A9 |\
wdenk9dd41a72005-05-12 22:48:09 +0000466 ORxS_NUMR_12)
467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
wdenk9dd41a72005-05-12 22:48:09 +0000469 PSDMR_BSMA_A15_A17 |\
Sergej Stepanov6abd82e2007-10-17 11:18:42 +0200470 PSDMR_SDA10_PBI0_A10 |\
wdenk9dd41a72005-05-12 22:48:09 +0000471 PSDMR_RFRC_5_CLK |\
472 PSDMR_PRETOACT_2W |\
473 PSDMR_ACTTORW_2W |\
474 PSDMR_BL |\
475 PSDMR_LDOTOPRE_2C |\
476 PSDMR_WRC_3C |\
477 PSDMR_CL_3)
478
479/* Bank 3 - UART
480*/
481
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
483#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
wdenk9dd41a72005-05-12 22:48:09 +0000484
485#endif /* __CONFIG_H */