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Tom Rixe63e5902009-10-17 12:41:06 -05001/*
2 * (C) Copyright 2006-2009
3 * Texas Instruments Incorporated.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * Nishanth Menon <nm@ti.com>
7 *
8 * Configuration settings for the 3430 TI SDP3430 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* TODO: REMOVE THE FOLLOWING
33 * Retained the following till size.h is removed in u-boot
34 */
35#include <asm/sizes.h>
36/*
37 * High Level Configuration Options
38 */
Tom Rixe63e5902009-10-17 12:41:06 -050039#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP34XX 1 /* which is a 34XX */
41#define CONFIG_OMAP3430 1 /* which is in a 3430 */
42#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
43
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040044#define CONFIG_SDRC /* The chip has SDRC controller */
45
Tom Rixe63e5902009-10-17 12:41:06 -050046#include <asm/arch/cpu.h> /* get chip and board defs */
47#include <asm/arch/omap3.h>
48
49/*
50 * NOTE: these #defines presume standard SDP jumper settings.
51 * In particular:
52 * - 26 MHz clock (not 19.2 or 38.4 MHz)
53 * - Boot from 128MB NOR, not NAND or OneNAND
54 *
55 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
56 * support for all the flash types the board supports.
57 */
58#define CONFIG_DISPLAY_CPUINFO 1
59#define CONFIG_DISPLAY_BOARDINFO 1
60
61/* Clock Defines */
62#define V_OSCK 26000000 /* Clock output from T2 */
63#define V_SCLK (V_OSCK >> 1)
64
65#undef CONFIG_USE_IRQ /* no support for IRQs */
66#define CONFIG_MISC_INIT_R
67
68#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
69#define CONFIG_SETUP_MEMORY_TAGS 1
70#define CONFIG_INITRD_TAG 1
71#define CONFIG_REVISION_TAG 1
72
Grant Likely2fa8ca92011-03-28 09:59:07 +000073#define CONFIG_OF_LIBFDT 1
74
Tom Rixe63e5902009-10-17 12:41:06 -050075/*
76 * Size of malloc() pool
77 * Total Size Environment - 256k
78 * Malloc - add 256k
79 */
80#define CONFIG_ENV_SIZE (256 << 10)
81#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
Tom Rixe63e5902009-10-17 12:41:06 -050082
83/*--------------------------------------------------------------------------*/
84
85/*
86 * Hardware drivers
87 */
88
89/*
90 * TWL4030
91 */
92#define CONFIG_TWL4030_POWER 1
93
94/*
95 * serial port - NS16550 compatible
96 */
97#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
98
99#define CONFIG_SYS_NS16550
100#define CONFIG_SYS_NS16550_SERIAL
101#define CONFIG_SYS_NS16550_REG_SIZE (-4)
102#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
103
104/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
105 * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
106 * support UART boot (that's only for UART3); it prevents sharing a Linux
107 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
108 *
109 * UART boot uses UART3 on J9, and the SDP user's guide says to use
110 * that for console. Downsides of using J9: you can't use IRDA too;
111 * since UART3 isn't in the CORE power domain, it may be a bit less
112 * usable in certain PM-sensitive debug scenarios.
113 */
114#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
115
116#ifdef CONSOLE_J9
117#define CONFIG_CONS_INDEX 3
118#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
119#define CONFIG_SERIAL3 3 /* UART3 */
120#else
121#define CONFIG_CONS_INDEX 1
122#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
123#define CONFIG_SERIAL1 1 /* UART1 */
124#endif
125
126#define CONFIG_ENV_OVERWRITE
127#define CONFIG_BAUDRATE 115200
128#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
129 115200}
130
131/*
132 * I2C for power management setup
133 */
134#define CONFIG_HARD_I2C 1
135#define CONFIG_SYS_I2C_SPEED 100000
136#define CONFIG_SYS_I2C_SLAVE 1
137#define CONFIG_SYS_I2C_BUS 0
138#define CONFIG_SYS_I2C_BUS_SELECT 1
139#define CONFIG_DRIVER_OMAP34XX_I2C 1
140
Nishanth Menon30563a02009-11-07 10:51:24 -0500141/* DDR - I use Infineon DDR */
142#define CONFIG_OMAP3_INFINEON_DDR 1
143
Tom Rixe63e5902009-10-17 12:41:06 -0500144/* OMITTED: single 1 Gbit MT29F1G NAND flash */
145
146/*
147 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
148 */
149#define CONFIG_SYS_FLASH_BASE 0x10000000
150#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
151#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
152#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
153#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
154#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
155#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
156#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
157
158#define CONFIG_SYS_FLASH_CFI_WIDTH 2
159#define PHYS_FLASH_SIZE (128 << 20)
160#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
161
Tom Rixe63e5902009-10-17 12:41:06 -0500162/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
163
164#define CONFIG_ENV_IS_IN_FLASH 1
165#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
166#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
167#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
168/*--------------------------------------------------------------------------*/
169
170/* commands to include */
171#include <config_cmd_default.h>
172
173/* Enabled commands */
174#define CONFIG_CMD_DHCP /* DHCP Support */
175#define CONFIG_CMD_EXT2 /* EXT2 Support */
176#define CONFIG_CMD_FAT /* FAT support */
177#define CONFIG_CMD_I2C /* I2C serial bus support */
178#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
179#define CONFIG_CMD_MMC /* MMC support */
180#define CONFIG_CMD_NET
181
182/* Disabled commands */
183#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
184#undef CONFIG_CMD_IMLS /* List all found images */
185
186/*--------------------------------------------------------------------------*/
187/*
188 * MMC boot support
189 */
190
191#if defined(CONFIG_CMD_MMC)
Tom Rini7cc862b2011-09-03 21:52:21 -0400192#define CONFIG_GENERIC_MMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500193#define CONFIG_MMC 1
Tom Rini7cc862b2011-09-03 21:52:21 -0400194#define CONFIG_OMAP_HSMMC 1
Tom Rixe63e5902009-10-17 12:41:06 -0500195#define CONFIG_DOS_PARTITION 1
196#endif
197
198/*----------------------------------------------------------------------------
199 * SMSC9115 Ethernet from SMSC9118 family
200 *----------------------------------------------------------------------------
201 */
202#if defined(CONFIG_CMD_NET)
203
Nishanth Menona1725992009-10-16 00:06:36 -0500204#define CONFIG_LAN91C96
Tom Rixe63e5902009-10-17 12:41:06 -0500205#define CONFIG_LAN91C96_BASE DEBUG_BASE
206#define CONFIG_LAN91C96_EXT_PHY
207
208#define CONFIG_BOOTP_SEND_HOSTNAME
209/*
210 * BOOTP fields
211 */
212#define CONFIG_BOOTP_SUBNETMASK 0x00000001
213#define CONFIG_BOOTP_GATEWAY 0x00000002
214#define CONFIG_BOOTP_HOSTNAME 0x00000004
215#define CONFIG_BOOTP_BOOTPATH 0x00000010
216#endif /* (CONFIG_CMD_NET) */
217
218/*
219 * Environment setup
220 *
221 * Default boot order: mmc bootscript, MMC uImage, NOR image.
222 * Network booting environment must be configured at site.
223 */
224
225/* allow overwriting serial config and ethaddr */
226#define CONFIG_ENV_OVERWRITE
227
228#define CONFIG_EXTRA_ENV_SETTINGS \
229 "loadaddr=0x82000000\0" \
230 "console=ttyS0,115200n8\0" \
231 "mmcargs=setenv bootargs console=${console} " \
232 "root=/dev/mmcblk0p2 rw " \
233 "rootfstype=ext3 rootwait\0" \
234 "norargs=setenv bootargs console=${console} " \
235 "root=/dev/mtdblock3 rw " \
236 "rootfstype=jffs2\0" \
237 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
238 "bootscript=echo Running bootscript from MMC/SD ...; " \
239 "autoscr ${loadaddr}\0" \
240 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
241 "mmcboot=echo Booting from MMC/SD ...; " \
242 "run mmcargs; " \
243 "bootm ${loadaddr}\0" \
244 "norboot=echo Booting from NOR ...; " \
245 "run norargs; " \
246 "bootm 0x80000\0" \
247
248#define CONFIG_BOOTCOMMAND \
249 "if mmcinit; then " \
250 "if run loadbootscript; then " \
251 "run bootscript; " \
252 "else " \
253 "if run loaduimage; then " \
254 "run mmcboot; " \
255 "else run norboot; " \
256 "fi; " \
257 "fi; " \
258 "else run norboot; fi"
259
260#define CONFIG_AUTO_COMPLETE 1
261
262/*--------------------------------------------------------------------------*/
263
264/*
265 * Miscellaneous configurable options
266 */
Tom Rixe63e5902009-10-17 12:41:06 -0500267
268#define CONFIG_SYS_LONGHELP /* undef to save memory */
269#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
270#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500271#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
Vaibhav Hiremathf62b1252011-09-03 21:24:19 -0400272#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Tom Rixe63e5902009-10-17 12:41:06 -0500273/* Print Buffer Size */
274#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
275 sizeof(CONFIG_SYS_PROMPT) + 16)
276#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
277/* Boot Argument Buffer Size */
278#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
279
280/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
281 * a basic sanity check ONLY
282 * IF you would like to increase coverage, increase the end address
283 * or run the test with custom options
284 */
285#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
286#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
287
288/* Default load address */
289#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
290
291/*--------------------------------------------------------------------------*/
292
293/*
294 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
295 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
296 */
297#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
298#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
299#define CONFIG_SYS_HZ 1000
300
301/*
302 * Stack sizes
303 *
304 * The stack sizes are set up in start.S using the settings below
305 */
306#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
307#ifdef CONFIG_USE_IRQ
308#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
309#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
310#endif
311
Dirk Behme5ec789f2010-11-30 11:10:40 -0500312#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
313#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
314#define CONFIG_SYS_INIT_RAM_SIZE 0x800
315#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
316 CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
Tom Rixe63e5902009-10-17 12:41:06 -0500318/*
319 * SDRAM Memory Map
320 */
321#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
322#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
323#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
324#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
325
326/* SDRAM Bank Allocation method */
327#define SDRC_R_B_C 1
328
329/*--------------------------------------------------------------------------*/
330
331/*
332 * NOR FLASH usage ... default nCS0:
333 * - one 256KB sector for U-Boot
334 * - one 256KB sector for its parameters (not all used)
335 * - eight sectors (2 MB) for kernel
336 * - rest for JFFS2
337 */
338
339/* Monitor at start of flash */
340#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
341#define CONFIG_SYS_MONITOR_LEN (256 << 10)
342
Tom Rixe63e5902009-10-17 12:41:06 -0500343/*
344 * NAND FLASH usage ... default nCS1:
345 * - four 128KB sectors for X-Loader
346 * - four 128KB sectors for U-Boot
347 * - two 128KB sector for its parameters
348 * - 32 sectors (4 MB) for kernel
349 * - rest for filesystem
350 */
351
352/*
353 * OneNAND FLASH usage ... default nCS2:
354 * - four 128KB sectors for X-Loader
355 * - two 128KB sectors for U-Boot
356 * - one 128KB sector for its parameters
357 * - sixteen sectors (2 MB) for kernel
358 * - rest for filesystem
359 */
360
Tom Rixe63e5902009-10-17 12:41:06 -0500361#endif /* __CONFIG_H */