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Michal Simek293eb332013-04-22 14:56:49 +02001/*
Michal Simekd9ae52c2015-11-30 16:13:03 +01002 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek293eb332013-04-22 14:56:49 +02003 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek293eb332013-04-22 14:56:49 +02007 */
8
9#include <common.h>
Michal Simekd9ae52c2015-11-30 16:13:03 +010010#include <dm.h>
Michal Simek345d3c02014-02-24 11:16:31 +010011#include <fdtdec.h>
12#include <libfdt.h>
Michal Simek293eb332013-04-22 14:56:49 +020013#include <malloc.h>
14#include <sdhci.h>
Michal Simek293eb332013-04-22 14:56:49 +020015
Siva Durga Prasad Paladugua57a4a52016-01-05 12:21:04 +053016#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
17# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
18#endif
19
Simon Glass329a4492016-07-05 17:10:15 -060020struct arasan_sdhci_plat {
21 struct mmc_config cfg;
22 struct mmc mmc;
23};
24
Michal Simekd9ae52c2015-11-30 16:13:03 +010025static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek293eb332013-04-22 14:56:49 +020026{
Simon Glass329a4492016-07-05 17:10:15 -060027 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simekd9ae52c2015-11-30 16:13:03 +010028 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
29 struct sdhci_host *host = dev_get_priv(dev);
Simon Glass329a4492016-07-05 17:10:15 -060030 u32 caps;
31 int ret;
Michal Simek293eb332013-04-22 14:56:49 +020032
Siva Durga Prasad Paladugueddabd12014-07-08 15:31:04 +053033 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladuguf9ec45d2014-01-22 09:17:09 +010034 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugub2156142016-01-12 15:12:16 +053035
36#ifdef CONFIG_ZYNQ_HISPD_BROKEN
37 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
38#endif
39
Michal Simek293eb332013-04-22 14:56:49 +020040 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
41
Simon Glass329a4492016-07-05 17:10:15 -060042 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
43 ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
44 caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
45 CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version,
46 host->quirks, 0);
47 host->mmc = &plat->mmc;
48 if (ret)
49 return ret;
50 host->mmc->priv = host;
Simon Glasscffe5d82016-05-01 13:52:34 -060051 host->mmc->dev = dev;
Simon Glass329a4492016-07-05 17:10:15 -060052 upriv->mmc = host->mmc;
Michal Simekd9ae52c2015-11-30 16:13:03 +010053
Simon Glass329a4492016-07-05 17:10:15 -060054 return sdhci_probe(dev);
Michal Simek293eb332013-04-22 14:56:49 +020055}
Michal Simekd9ae52c2015-11-30 16:13:03 +010056
57static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
58{
59 struct sdhci_host *host = dev_get_priv(dev);
60
Masahiro Yamadacacd1d22016-04-22 20:59:31 +090061 host->name = dev->name;
Michal Simekd9ae52c2015-11-30 16:13:03 +010062 host->ioaddr = (void *)dev_get_addr(dev);
63
64 return 0;
65}
66
Simon Glass329a4492016-07-05 17:10:15 -060067static int arasan_sdhci_bind(struct udevice *dev)
68{
69 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
70 int ret;
71
72 ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
73 if (ret)
74 return ret;
75
76 return 0;
77}
78
Michal Simekd9ae52c2015-11-30 16:13:03 +010079static const struct udevice_id arasan_sdhci_ids[] = {
80 { .compatible = "arasan,sdhci-8.9a" },
81 { }
82};
83
84U_BOOT_DRIVER(arasan_sdhci_drv) = {
85 .name = "arasan_sdhci",
86 .id = UCLASS_MMC,
87 .of_match = arasan_sdhci_ids,
88 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass329a4492016-07-05 17:10:15 -060089 .ops = &sdhci_ops,
90 .bind = arasan_sdhci_bind,
Michal Simekd9ae52c2015-11-30 16:13:03 +010091 .probe = arasan_sdhci_probe,
92 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Simon Glass329a4492016-07-05 17:10:15 -060093 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simekd9ae52c2015-11-30 16:13:03 +010094};