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Wolfgang Denk0c8721a2005-09-23 11:05:55 +02001 AMCC Ebony Board
wdenkc6097192002-11-03 00:24:07 +00002
wdenk8bde7f72003-06-27 21:31:46 +00003 Last Update: September 12, 2002
wdenkc6097192002-11-03 00:24:07 +00004=======================================================================
5
Wolfgang Denk0c8721a2005-09-23 11:05:55 +02006This file contains some handy info regarding U-Boot and the AMCC
wdenkc6097192002-11-03 00:24:07 +00007Ebony evalutation board. See the README.ppc440 for additional
8information.
9
10
11SWITCH SETTINGS & JUMPERS
12==========================
13
14Here's what I've been using successfully. If you feel inclined to
15change things ... please read the docs!
16
17DIPSW U46 U80
18------------------------
19SW 1 off on
20SW 2 on on
21SW 3 on on
22SW 4 off on
23SW 5 on off
24SW 6 on on
25SW 7 on off
26SW 8 on off
27
28J41: strapped
29J42: open
30
31All others are factory default.
32
33
Peter Tyser0f89c542009-04-18 22:34:03 -050034I2C probe
wdenkc6097192002-11-03 00:24:07 +000035=====================
36
37The i2c utilities have been tested on both Rev B. and Rev C. and
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
wdenkc6097192002-11-03 00:24:07 +000039probing the CDCV850 clock controller at address 0x69 (since reading
40it causes the i2c implementation to misbehave. The output of
Peter Tyser0f89c542009-04-18 22:34:03 -050041'i2c probe' should look like this (assuming you are only using a single
wdenkc6097192002-11-03 00:24:07 +000042SO-DIMM:
43
Peter Tyser0f89c542009-04-18 22:34:03 -050044=> i2c probe
wdenkc6097192002-11-03 00:24:07 +000045Valid chip addresses: 50 53 54
46Excluded chip addresses: 69
47
48
49GETTING OUT OF I2C TROUBLE
50===========================
51
52If you're like me ... you may have screwed up your bootstrap serial
53eeprom ... or worse, your SPD eeprom when experimenting with the
54i2c commands. If so, here are some ideas on how to get out of
55trouble:
56
57Serial bootstrap eeprom corruption:
58-----------------------------------
59Power down the board and set the following straps:
60
61J41 - open
62J42 - strapped
63
64This will select the default sys0 and sys1 settings (the serial
65eeproms are not used). Then power up the board and fix the serial
Peter Tyser0f89c542009-04-18 22:34:03 -050066eeprom using the 'i2c mm' command. Here are the values I currently
wdenkc6097192002-11-03 00:24:07 +000067use:
68
Peter Tyser0f89c542009-04-18 22:34:03 -050069=> i2c md 50 0 10
wdenkc6097192002-11-03 00:24:07 +0000700000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
71
Peter Tyser0f89c542009-04-18 22:34:03 -050072=> i2c md 54 0 10
wdenkc6097192002-11-03 00:24:07 +0000730000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
74
75Once you have the eeproms set correctly change the
76J41/J42 straps as you desire.
77
78SPD eeprom corruption:
79------------------------
80I've corrupted the SPD eeprom several times ... perhaps too much coffee
81and not enough presence of mind ;-). By default, the ebony code uses
82the SPD to initialize the DDR SDRAM control registers. So if the SPD
83eeprom is corrupted, U-Boot will never get into ram. Here's how I got
84out of this situation:
85
Peter Tyser0f89c542009-04-18 22:34:03 -0500860. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
87use 'i2c md' to capture the various device contents to a file. Some day
wdenkc6097192002-11-03 00:24:07 +000088you may be glad you did this ... trust me :-). Otherwise try the
89following:
90
911. In the include/configs/EBONY.h file find the line that defines
92the CONFIG_SPD_EEPROM macro and undefine it. E.g:
93
94#undef CONFIG_SPD_EEPROM
95
96This will make the code use default SDRAM control register
97settings without using the SPD eeprom.
98
992. Rebuild U-Boot
100
1013. Load the new U-Boot image and reboot ebony.
102
Peter Tyser0f89c542009-04-18 22:34:03 -05001034. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
wdenkc6097192002-11-03 00:24:07 +0000104contents that work with the default SO-DIMM that comes with the
105ebony board (micron 8VDDT164AG-265A1). Note: these are probably
106_not_ the factory settings ... but they work.
107
Peter Tyser0f89c542009-04-18 22:34:03 -0500108=> i2c md 53 0 10 80
wdenkc6097192002-11-03 00:24:07 +00001090000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu.....
1100010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
1110020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
1120030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
1130040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
1140050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
1150060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
1160070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
117
118
119PCI DOUBLE-ENUMERATION WOES
120===========================
121
122If you're not using PCI-X cards and are simply using 32-bit and/or
12333 MHz cards via extenders and the like, you may notice that the
124initial pci scan reports various devices twice ... and configuration
125does not succeed (one or more devices are enumerated twice). To correct
126this we replaced the 2K ohm resistor on the IDSEL line(s) with a
12722 ohm resistor and the problem went away. This change hasn't broken
128anything yet -- use at your own risk.
129
130We never tested anything other than 33 MHz/32-bit cards. If you have
131the chance to do this, please let me know how things turn out :-)
132
133
wdenkc6097192002-11-03 00:24:07 +0000134Regards,
135--Scott
136<smcnutt@artesyncp.com>