wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | * |
| 23 | * |
| 24 | * TODO: clean-up |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? |
| 29 | * |
| 30 | * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being |
| 31 | * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum |
| 32 | * parameters from the datasheet are: |
| 33 | * Tclk = 7.5ns (CL = 2) |
| 34 | * Trp = 15ns |
| 35 | * Trc = 60ns |
| 36 | * Trcd = 15ns |
| 37 | * Trfc = 66ns |
| 38 | * |
| 39 | * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock |
| 40 | * period is 10ns and the parameters needed for the Timing Register are: |
| 41 | * CASL = CL = 2 clock cycles |
| 42 | * PTA = Trp = 15ns / 10ns = 2 clock cycles |
| 43 | * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles |
| 44 | * LDF = 2 clock cycles (but can be extended to meet board-level timing) |
| 45 | * RFTA = Trfc = 66ns / 10ns= 7 clock cycles |
| 46 | * RCD = Trcd = 15ns / 10ns= 2 clock cycles |
| 47 | * |
| 48 | * The actual bit settings in the register would be: |
| 49 | * |
| 50 | * CASL = 0b01 |
| 51 | * PTA = 0b01 |
| 52 | * CTP = 0b10 |
| 53 | * LDF = 0b01 |
| 54 | * RFTA = 0b011 |
| 55 | * RCD = 0b01 |
| 56 | * |
| 57 | * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc |
| 58 | * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay |
| 59 | * defined as Trc rather than Trfc. |
| 60 | * When using DIMM modules, most but not all of the required timing parameters can be read |
| 61 | * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc |
| 62 | * are not available from the EEPROM |
| 63 | */ |
| 64 | |
| 65 | #include <common.h> |
| 66 | #include "mip405.h" |
| 67 | #include <asm/processor.h> |
| 68 | #include <405gp_i2c.h> |
| 69 | #include <miiphy.h> |
| 70 | #include "../common/common_util.h" |
| 71 | #include <i2c.h> |
| 72 | extern block_dev_desc_t * scsi_get_dev(int dev); |
| 73 | extern block_dev_desc_t * ide_get_dev(int dev); |
| 74 | |
| 75 | #undef SDRAM_DEBUG |
| 76 | |
| 77 | #define FALSE 0 |
| 78 | #define TRUE 1 |
| 79 | |
| 80 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ |
| 81 | #ifndef __ldiv_t_defined |
| 82 | typedef struct { |
| 83 | long int quot; /* Quotient */ |
| 84 | long int rem; /* Remainder */ |
| 85 | } ldiv_t; |
| 86 | extern ldiv_t ldiv (long int __numer, long int __denom); |
| 87 | # define __ldiv_t_defined 1 |
| 88 | #endif |
| 89 | |
| 90 | |
| 91 | #define PLD_PART_REG PER_PLD_ADDR + 0 |
| 92 | #define PLD_VERS_REG PER_PLD_ADDR + 1 |
| 93 | #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 |
| 94 | #define PLD_IRQ_REG PER_PLD_ADDR + 3 |
| 95 | #define PLD_COM_MODE_REG PER_PLD_ADDR + 4 |
| 96 | #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 |
| 97 | |
| 98 | #define MEGA_BYTE (1024*1024) |
| 99 | |
| 100 | typedef struct { |
| 101 | unsigned char boardtype; /* Board revision and Population Options */ |
| 102 | unsigned char cal; /* cas Latency (will be programmend as cal-1) */ |
| 103 | unsigned char trp; /* datain27 in clocks */ |
| 104 | unsigned char trcd; /* datain29 in clocks */ |
| 105 | unsigned char tras; /* datain30 in clocks */ |
| 106 | unsigned char tctp; /* tras - trcd in clocks */ |
| 107 | unsigned char am; /* Address Mod (will be programmed as am-1) */ |
| 108 | unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ |
| 109 | unsigned char ecc; /* if true, ecc is enabled */ |
| 110 | } sdram_t; |
| 111 | |
| 112 | const sdram_t sdram_table[] = { |
| 113 | { 0x0f, /* Rev A, 128MByte -1 Board */ |
| 114 | 3, /* Case Latenty = 3 */ |
| 115 | 3, /* trp 20ns / 7.5 ns datain[27] */ |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 116 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
| 117 | 6, /* tras 44ns /7.5 ns (datain[30]) */ |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 118 | 4, /* tcpt 44 - 20ns = 24ns */ |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 119 | 3, /* Address Mode = 3 */ |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 120 | 5, /* size value */ |
| 121 | 1}, /* ECC enabled */ |
| 122 | { 0x07, /* Rev A, 64MByte -2 Board */ |
| 123 | 3, /* Case Latenty = 3 */ |
| 124 | 3, /* trp 20ns / 7.5 ns datain[27] */ |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 125 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
| 126 | 6, /* tras 44ns /7.5 ns (datain[30]) */ |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 127 | 4, /* tcpt 44 - 20ns = 24ns */ |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 128 | 2, /* Address Mode = 2 */ |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 129 | 4, /* size value */ |
| 130 | 1}, /* ECC enabled */ |
wdenk | 3e38691 | 2003-04-05 00:53:31 +0000 | [diff] [blame] | 131 | { 0x03, /* Rev A, 128MByte -4 Board */ |
| 132 | 3, /* Case Latenty = 3 */ |
| 133 | 3, /* trp 20ns / 7.5 ns datain[27] */ |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 134 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
| 135 | 6, /* tras 44ns /7.5 ns (datain[30]) */ |
wdenk | 3e38691 | 2003-04-05 00:53:31 +0000 | [diff] [blame] | 136 | 4, /* tcpt 44 - 20ns = 24ns */ |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 137 | 3, /* Address Mode = 3 */ |
| 138 | 5, /* size value */ |
| 139 | 1}, /* ECC enabled */ |
| 140 | { 0x1f, /* Rev B, 128MByte -3 Board */ |
| 141 | 3, /* Case Latenty = 3 */ |
| 142 | 3, /* trp 20ns / 7.5 ns datain[27] */ |
| 143 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
| 144 | 6, /* tras 44ns /7.5 ns (datain[30]) */ |
| 145 | 4, /* tcpt 44 - 20ns = 24ns */ |
| 146 | 3, /* Address Mode = 3 */ |
wdenk | 3e38691 | 2003-04-05 00:53:31 +0000 | [diff] [blame] | 147 | 5, /* size value */ |
| 148 | 1}, /* ECC enabled */ |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 149 | { 0xff, /* terminator */ |
| 150 | 0xff, |
| 151 | 0xff, |
| 152 | 0xff, |
| 153 | 0xff, |
| 154 | 0xff, |
| 155 | 0xff, |
| 156 | 0xff } |
| 157 | }; |
| 158 | |
| 159 | void SDRAM_err (const char *s) |
| 160 | { |
| 161 | #ifndef SDRAM_DEBUG |
| 162 | DECLARE_GLOBAL_DATA_PTR; |
| 163 | |
| 164 | (void) get_clocks (); |
| 165 | gd->baudrate = 9600; |
| 166 | serial_init (); |
| 167 | #endif |
| 168 | serial_puts ("\n"); |
| 169 | serial_puts (s); |
| 170 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); |
| 171 | for (;;); |
| 172 | } |
| 173 | |
| 174 | |
| 175 | unsigned char get_board_revcfg (void) |
| 176 | { |
| 177 | out8 (PER_BOARD_ADDR, 0); |
| 178 | return (in8 (PER_BOARD_ADDR)); |
| 179 | } |
| 180 | |
| 181 | |
| 182 | #ifdef SDRAM_DEBUG |
| 183 | |
| 184 | void write_hex (unsigned char i) |
| 185 | { |
| 186 | char cc; |
| 187 | |
| 188 | cc = i >> 4; |
| 189 | cc &= 0xf; |
| 190 | if (cc > 9) |
| 191 | serial_putc (cc + 55); |
| 192 | else |
| 193 | serial_putc (cc + 48); |
| 194 | cc = i & 0xf; |
| 195 | if (cc > 9) |
| 196 | serial_putc (cc + 55); |
| 197 | else |
| 198 | serial_putc (cc + 48); |
| 199 | } |
| 200 | |
| 201 | void write_4hex (unsigned long val) |
| 202 | { |
| 203 | write_hex ((unsigned char) (val >> 24)); |
| 204 | write_hex ((unsigned char) (val >> 16)); |
| 205 | write_hex ((unsigned char) (val >> 8)); |
| 206 | write_hex ((unsigned char) val); |
| 207 | } |
| 208 | |
| 209 | #endif |
| 210 | |
| 211 | |
| 212 | int init_sdram (void) |
| 213 | { |
| 214 | DECLARE_GLOBAL_DATA_PTR; |
| 215 | |
| 216 | unsigned long tmp, baseaddr; |
| 217 | unsigned short i; |
| 218 | unsigned char trp_clocks, |
| 219 | trcd_clocks, |
| 220 | tras_clocks, |
| 221 | trc_clocks, |
| 222 | tctp_clocks; |
| 223 | unsigned char cal_val; |
| 224 | unsigned char bc; |
| 225 | unsigned long pbcr, sdram_tim, sdram_bank; |
| 226 | unsigned long *p; |
| 227 | |
| 228 | i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); |
| 229 | (void) get_clocks (); |
| 230 | gd->baudrate = 9600; |
| 231 | serial_init (); |
| 232 | serial_puts ("\nInitializing SDRAM, Please stand by"); |
| 233 | mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ |
| 234 | pbcr = mfdcr (ebccfgd); |
| 235 | if ((pbcr & 0x00002000) == 0) { |
| 236 | /* MPS Boot, set up the flash */ |
| 237 | mtdcr (ebccfga, pb1ap); |
| 238 | mtdcr (ebccfgd, FLASH_AP); |
| 239 | mtdcr (ebccfga, pb1cr); |
| 240 | mtdcr (ebccfgd, FLASH_CR); |
| 241 | } else { |
| 242 | /* Flash boot, set up the MPS */ |
| 243 | mtdcr (ebccfga, pb1ap); |
| 244 | mtdcr (ebccfgd, MPS_AP); |
| 245 | mtdcr (ebccfga, pb1cr); |
| 246 | mtdcr (ebccfgd, MPS_CR); |
| 247 | } |
| 248 | /* set up UART0 (CS2) and UART1 (CS3) */ |
| 249 | mtdcr (ebccfga, pb2ap); |
| 250 | mtdcr (ebccfgd, UART0_AP); |
| 251 | mtdcr (ebccfga, pb2cr); |
| 252 | mtdcr (ebccfgd, UART0_CR); |
| 253 | mtdcr (ebccfga, pb3ap); |
| 254 | mtdcr (ebccfgd, UART1_AP); |
| 255 | mtdcr (ebccfga, pb3cr); |
| 256 | mtdcr (ebccfgd, UART1_CR); |
| 257 | |
| 258 | /* set up the pld */ |
| 259 | mtdcr (ebccfga, pb7ap); |
| 260 | mtdcr (ebccfgd, PLD_AP); |
| 261 | mtdcr (ebccfga, pb7cr); |
| 262 | mtdcr (ebccfgd, PLD_CR); |
| 263 | /* set up the board rev reg */ |
| 264 | mtdcr (ebccfga, pb5ap); |
| 265 | mtdcr (ebccfgd, BOARD_AP); |
| 266 | mtdcr (ebccfga, pb5cr); |
| 267 | mtdcr (ebccfgd, BOARD_CR); |
| 268 | |
| 269 | |
| 270 | #ifdef SDRAM_DEBUG |
| 271 | out8 (PER_BOARD_ADDR, 0); |
| 272 | bc = in8 (PER_BOARD_ADDR); |
| 273 | serial_puts ("\nBoard Rev: "); |
| 274 | write_hex (bc); |
| 275 | serial_puts (" (PLD="); |
| 276 | bc = in8 (PLD_BOARD_CFG_REG); |
| 277 | write_hex (bc); |
| 278 | serial_puts (")\n"); |
| 279 | #endif |
| 280 | bc = get_board_revcfg (); |
| 281 | #ifdef SDRAM_DEBUG |
| 282 | serial_puts ("\nstart SDRAM Setup\n"); |
| 283 | serial_puts ("\nBoard Rev: "); |
| 284 | write_hex (bc); |
| 285 | serial_puts ("\n"); |
| 286 | #endif |
| 287 | i = 0; |
| 288 | baseaddr = CFG_SDRAM_BASE; |
| 289 | while (sdram_table[i].sz != 0xff) { |
| 290 | if (sdram_table[i].boardtype == bc) |
| 291 | break; |
| 292 | i++; |
| 293 | } |
| 294 | if (sdram_table[i].boardtype != bc) |
| 295 | SDRAM_err ("No SDRAM table found for this board!!!\n"); |
| 296 | #ifdef SDRAM_DEBUG |
| 297 | serial_puts (" found table "); |
| 298 | write_hex (i); |
| 299 | serial_puts (" \n"); |
| 300 | #endif |
| 301 | cal_val = sdram_table[i].cal - 1; /* Cas Latency */ |
| 302 | trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ |
| 303 | trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ |
| 304 | tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ |
| 305 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ |
| 306 | tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ |
| 307 | /* trc_clocks is sum of trp_clocks + tras_clocks */ |
| 308 | trc_clocks = trp_clocks + tras_clocks; |
| 309 | /* get SDRAM timing register */ |
| 310 | mtdcr (memcfga, mem_sdtr1); |
| 311 | sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; |
| 312 | /* insert CASL value */ |
| 313 | sdram_tim |= ((unsigned long) (cal_val)) << 23; |
| 314 | /* insert PTA value */ |
| 315 | sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; |
| 316 | /* insert CTP value */ |
| 317 | sdram_tim |= |
| 318 | ((unsigned long) (trc_clocks - trp_clocks - |
| 319 | trcd_clocks)) << 16; |
| 320 | /* insert LDF (always 01) */ |
| 321 | sdram_tim |= ((unsigned long) 0x01) << 14; |
| 322 | /* insert RFTA value */ |
| 323 | sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; |
| 324 | /* insert RCD value */ |
| 325 | sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; |
| 326 | |
| 327 | tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ |
| 328 | /* insert SZ value; */ |
| 329 | tmp |= ((unsigned long) sdram_table[i].sz << 17); |
| 330 | /* get SDRAM bank 0 register */ |
| 331 | mtdcr (memcfga, mem_mb0cf); |
| 332 | sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; |
| 333 | sdram_bank |= (baseaddr | tmp | 0x01); |
| 334 | |
| 335 | #ifdef SDRAM_DEBUG |
| 336 | serial_puts ("sdtr: "); |
| 337 | write_4hex (sdram_tim); |
| 338 | serial_puts ("\n"); |
| 339 | #endif |
| 340 | |
| 341 | /* write SDRAM timing register */ |
| 342 | mtdcr (memcfga, mem_sdtr1); |
| 343 | mtdcr (memcfgd, sdram_tim); |
| 344 | |
| 345 | #ifdef SDRAM_DEBUG |
| 346 | serial_puts ("mb0cf: "); |
| 347 | write_4hex (sdram_bank); |
| 348 | serial_puts ("\n"); |
| 349 | #endif |
| 350 | |
| 351 | /* write SDRAM bank 0 register */ |
| 352 | mtdcr (memcfga, mem_mb0cf); |
| 353 | mtdcr (memcfgd, sdram_bank); |
| 354 | |
| 355 | if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ |
| 356 | /* get SDRAM refresh interval register */ |
| 357 | mtdcr (memcfga, mem_rtr); |
| 358 | tmp = mfdcr (memcfgd) & ~0x3FF80000; |
| 359 | tmp |= 0x07F00000; |
| 360 | } else { |
| 361 | /* get SDRAM refresh interval register */ |
| 362 | mtdcr (memcfga, mem_rtr); |
| 363 | tmp = mfdcr (memcfgd) & ~0x3FF80000; |
| 364 | tmp |= 0x05F00000; |
| 365 | } |
| 366 | /* write SDRAM refresh interval register */ |
| 367 | mtdcr (memcfga, mem_rtr); |
| 368 | mtdcr (memcfgd, tmp); |
| 369 | /* enable ECC if used */ |
| 370 | #if 1 |
| 371 | if (sdram_table[i].ecc) { |
| 372 | /* disable checking for all banks */ |
| 373 | #ifdef SDRAM_DEBUG |
| 374 | serial_puts ("disable ECC.. "); |
| 375 | #endif |
| 376 | mtdcr (memcfga, mem_ecccf); |
| 377 | tmp = mfdcr (memcfgd); |
| 378 | tmp &= 0xff0fffff; /* disable all banks */ |
| 379 | mtdcr (memcfga, mem_ecccf); |
| 380 | /* set up SDRAM Controller with ECC enabled */ |
| 381 | #ifdef SDRAM_DEBUG |
| 382 | serial_puts ("setup SDRAM Controller.. "); |
| 383 | #endif |
| 384 | mtdcr (memcfgd, tmp); |
| 385 | mtdcr (memcfga, mem_mcopt1); |
| 386 | tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; |
| 387 | mtdcr (memcfga, mem_mcopt1); |
| 388 | mtdcr (memcfgd, tmp); |
| 389 | udelay (600); |
| 390 | #ifdef SDRAM_DEBUG |
| 391 | serial_puts ("fill the memory..\n"); |
| 392 | #endif |
| 393 | serial_puts ("."); |
| 394 | /* now, fill all the memory */ |
| 395 | tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); |
| 396 | p = (unsigned long) 0; |
| 397 | while ((unsigned long) p < tmp) { |
| 398 | *p++ = 0L; |
| 399 | if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ |
| 400 | serial_puts ("."); |
| 401 | |
| 402 | |
| 403 | } |
| 404 | /* enable bank 0 */ |
| 405 | serial_puts ("."); |
| 406 | #ifdef SDRAM_DEBUG |
| 407 | serial_puts ("enable ECC\n"); |
| 408 | #endif |
| 409 | udelay (400); |
| 410 | mtdcr (memcfga, mem_ecccf); |
| 411 | tmp = mfdcr (memcfgd); |
| 412 | tmp |= 0x00800000; /* enable bank 0 */ |
| 413 | mtdcr (memcfgd, tmp); |
| 414 | udelay (400); |
| 415 | } else |
| 416 | #endif |
| 417 | { |
| 418 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ |
| 419 | mtdcr (memcfga, mem_mcopt1); |
| 420 | tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; |
| 421 | mtdcr (memcfga, mem_mcopt1); |
| 422 | mtdcr (memcfgd, tmp); |
| 423 | udelay (400); |
| 424 | } |
| 425 | serial_puts ("\n"); |
| 426 | return (0); |
| 427 | } |
| 428 | |
| 429 | int board_pre_init (void) |
| 430 | { |
| 431 | init_sdram (); |
| 432 | |
| 433 | /*-------------------------------------------------------------------------+ |
| 434 | | Interrupt controller setup for the PIP405 board. |
| 435 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive |
| 436 | | IRQ 16 405GP internally generated; active low; level sensitive |
| 437 | | IRQ 17-24 RESERVED |
| 438 | | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive |
| 439 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive |
| 440 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive |
| 441 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive |
| 442 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive |
| 443 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive |
| 444 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive |
| 445 | | Note for MIP405 board: |
| 446 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that |
| 447 | | the Interrupt Controller in the South Bridge has caused the |
| 448 | | interrupt. The IC must be read to determine which device |
| 449 | | caused the interrupt. |
| 450 | | |
| 451 | +-------------------------------------------------------------------------*/ |
| 452 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 453 | mtdcr (uicer, 0x00000000); /* disable all ints */ |
| 454 | mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ |
| 455 | mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ |
| 456 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ |
| 457 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ |
| 458 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | |
| 463 | /* |
| 464 | * Get some PLD Registers |
| 465 | */ |
| 466 | |
| 467 | unsigned short get_pld_parvers (void) |
| 468 | { |
| 469 | unsigned short result; |
| 470 | unsigned char rc; |
| 471 | |
| 472 | rc = in8 (PLD_PART_REG); |
| 473 | result = (unsigned short) rc << 8; |
| 474 | rc = in8 (PLD_VERS_REG); |
| 475 | result |= rc; |
| 476 | return result; |
| 477 | } |
| 478 | |
| 479 | |
| 480 | |
| 481 | void user_led0 (unsigned char on) |
| 482 | { |
| 483 | if (on) |
| 484 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); |
| 485 | else |
| 486 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); |
| 487 | } |
| 488 | |
| 489 | |
| 490 | void ide_set_reset (int idereset) |
| 491 | { |
| 492 | /* if reset = 1 IDE reset will be asserted */ |
| 493 | if (idereset) |
| 494 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); |
| 495 | else { |
| 496 | udelay (10000); |
| 497 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | |
| 502 | /* ------------------------------------------------------------------------- */ |
| 503 | |
| 504 | /* |
| 505 | * Check Board Identity: |
| 506 | */ |
| 507 | |
| 508 | int checkboard (void) |
| 509 | { |
| 510 | unsigned char s[50]; |
| 511 | unsigned char bc, var, rc; |
| 512 | int i; |
| 513 | backup_t *b = (backup_t *) s; |
| 514 | |
| 515 | puts ("Board: "); |
| 516 | |
| 517 | bc = get_board_revcfg (); |
| 518 | var = ~bc; |
| 519 | var &= 0xf; |
| 520 | rc = 0; |
| 521 | for (i = 0; i < 4; i++) { |
| 522 | rc <<= 1; |
| 523 | rc += (var & 0x1); |
| 524 | var >>= 1; |
| 525 | } |
| 526 | rc++; |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 527 | if((((bc>>4) & 0xf)==0x1) /* Rev B PCB with */ |
| 528 | && (rc==0x1)) /* Population Option 1 is a -3 */ |
| 529 | rc=3; |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 530 | i = getenv_r ("serial#", s, 32); |
| 531 | if ((i == 0) || strncmp (s, "MIP405", 6)) { |
| 532 | get_backup_values (b); |
| 533 | if (strncmp (b->signature, "MPL\0", 4) != 0) { |
| 534 | puts ("### No HW ID - assuming MIP405"); |
| 535 | printf ("-%d Rev %c", rc, 'A' + ((bc >> 4) & 0xf)); |
| 536 | } else { |
| 537 | b->serial_name[6] = 0; |
| 538 | printf ("%s-%d Rev %c SN: %s", b->serial_name, rc, |
| 539 | 'A' + ((bc >> 4) & 0xf), &b->serial_name[7]); |
| 540 | } |
| 541 | } else { |
| 542 | s[6] = 0; |
| 543 | printf ("%s-%d Rev %c SN: %s", s, rc, 'A' + ((bc >> 4) & 0xf), |
| 544 | &s[7]); |
| 545 | } |
| 546 | bc = in8 (PLD_EXT_CONF_REG); |
| 547 | printf (" Boot Config: 0x%x\n", bc); |
| 548 | return (0); |
| 549 | } |
| 550 | |
| 551 | |
| 552 | /* ------------------------------------------------------------------------- */ |
| 553 | /* ------------------------------------------------------------------------- */ |
| 554 | /* |
| 555 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of |
| 556 | the necessary info for SDRAM controller configuration |
| 557 | */ |
| 558 | /* ------------------------------------------------------------------------- */ |
| 559 | /* ------------------------------------------------------------------------- */ |
| 560 | static int test_dram (unsigned long ramsize); |
| 561 | |
| 562 | long int initdram (int board_type) |
| 563 | { |
| 564 | |
| 565 | unsigned long bank_reg[4], tmp, bank_size; |
| 566 | int i, ds; |
| 567 | unsigned long TotalSize; |
| 568 | |
| 569 | ds = 0; |
| 570 | /* since the DRAM controller is allready set up, calculate the size with the |
| 571 | bank registers */ |
| 572 | mtdcr (memcfga, mem_mb0cf); |
| 573 | bank_reg[0] = mfdcr (memcfgd); |
| 574 | mtdcr (memcfga, mem_mb1cf); |
| 575 | bank_reg[1] = mfdcr (memcfgd); |
| 576 | mtdcr (memcfga, mem_mb2cf); |
| 577 | bank_reg[2] = mfdcr (memcfgd); |
| 578 | mtdcr (memcfga, mem_mb3cf); |
| 579 | bank_reg[3] = mfdcr (memcfgd); |
| 580 | TotalSize = 0; |
| 581 | for (i = 0; i < 4; i++) { |
| 582 | if ((bank_reg[i] & 0x1) == 0x1) { |
| 583 | tmp = (bank_reg[i] >> 17) & 0x7; |
| 584 | bank_size = 4 << tmp; |
| 585 | TotalSize += bank_size; |
| 586 | } else |
| 587 | ds = 1; |
| 588 | } |
| 589 | mtdcr (memcfga, mem_ecccf); |
| 590 | tmp = mfdcr (memcfgd); |
| 591 | |
| 592 | if (!tmp) |
| 593 | printf ("No "); |
| 594 | printf ("ECC "); |
| 595 | |
| 596 | test_dram (TotalSize * MEGA_BYTE); |
| 597 | return (TotalSize * MEGA_BYTE); |
| 598 | } |
| 599 | |
| 600 | /* ------------------------------------------------------------------------- */ |
| 601 | |
| 602 | extern int mem_test (unsigned long start, unsigned long ramsize, |
| 603 | int quiet); |
| 604 | |
| 605 | static int test_dram (unsigned long ramsize) |
| 606 | { |
| 607 | #ifdef SDRAM_DEBUG |
| 608 | mem_test (0L, ramsize, 1); |
| 609 | #endif |
| 610 | /* not yet implemented */ |
| 611 | return (1); |
| 612 | } |
| 613 | |
| 614 | int misc_init_r (void) |
| 615 | { |
| 616 | return (0); |
| 617 | } |
| 618 | |
| 619 | |
| 620 | void print_mip405_rev (void) |
| 621 | { |
| 622 | unsigned char part, vers, cfg, rev; |
| 623 | |
| 624 | cfg = get_board_revcfg (); |
| 625 | vers = cfg; |
| 626 | vers &= 0xf; |
| 627 | rev = (((vers & 0x1) ? 0x8 : 0) | |
| 628 | ((vers & 0x2) ? 0x4 : 0) | |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 629 | ((vers & 0x4) ? 0x2 : 0) | |
| 630 | ((vers & 0x8) ? 0x1 : 0)); |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 631 | |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 632 | vers=16-rev; |
| 633 | rev=vers; |
| 634 | if((rev==1) && ((cfg >> 4)==1)) /* Rev B PCB and -1 is a -3 */ |
| 635 | rev=3; |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 636 | part = in8 (PLD_PART_REG); |
| 637 | vers = in8 (PLD_VERS_REG); |
| 638 | printf ("Rev: MIP405-%d Rev %c PLD%d Vers %d\n", |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 639 | rev, ((cfg >> 4) & 0xf) + 'A', part, vers); |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 640 | } |
| 641 | |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 642 | extern void mem_test_reloc(void); |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 643 | |
| 644 | int last_stage_init (void) |
| 645 | { |
wdenk | 33149b8 | 2003-05-23 11:38:58 +0000 | [diff] [blame^] | 646 | mem_test_reloc(); |
wdenk | 3e38691 | 2003-04-05 00:53:31 +0000 | [diff] [blame] | 647 | /* write correct LED configuration */ |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 648 | if (miiphy_write (0x1, 0x14, 0x2402) != 0) { |
| 649 | printf ("Error writing to the PHY\n"); |
| 650 | } |
wdenk | 3e38691 | 2003-04-05 00:53:31 +0000 | [diff] [blame] | 651 | /* since LED/CFG2 is not connected on the -2, |
| 652 | * write to correct capability information */ |
| 653 | if (miiphy_write (0x1, 0x4, 0x01E1) != 0) { |
| 654 | printf ("Error writing to the PHY\n"); |
| 655 | } |
wdenk | 858b1a6 | 2002-09-30 16:12:23 +0000 | [diff] [blame] | 656 | print_mip405_rev (); |
| 657 | show_stdio_dev (); |
| 658 | check_env (); |
| 659 | return 0; |
| 660 | } |
| 661 | |
| 662 | /*************************************************************************** |
| 663 | * some helping routines |
| 664 | */ |
| 665 | |
| 666 | int overwrite_console (void) |
| 667 | { |
| 668 | return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */ |
| 669 | } |
| 670 | |
| 671 | |
| 672 | /************************************************************************ |
| 673 | * Print MIP405 Info |
| 674 | ************************************************************************/ |
| 675 | void print_mip405_info (void) |
| 676 | { |
| 677 | unsigned char part, vers, cfg, irq_reg, com_mode, ext; |
| 678 | |
| 679 | part = in8 (PLD_PART_REG); |
| 680 | vers = in8 (PLD_VERS_REG); |
| 681 | cfg = in8 (PLD_BOARD_CFG_REG); |
| 682 | irq_reg = in8 (PLD_IRQ_REG); |
| 683 | com_mode = in8 (PLD_COM_MODE_REG); |
| 684 | ext = in8 (PLD_EXT_CONF_REG); |
| 685 | |
| 686 | printf ("PLD Part %d version %d\n", part, vers); |
| 687 | printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); |
| 688 | printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, |
| 689 | (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); |
| 690 | printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); |
| 691 | printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); |
| 692 | printf ("Test ist %x\n", com_mode); |
| 693 | printf ("User Config Switch %d %d %d %d %d %d %d %d\n", |
| 694 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, |
| 695 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, |
| 696 | (ext >> 6) & 0x1, (ext >> 7) & 0x1); |
| 697 | printf ("SER1 uses handshakes %s\n", |
| 698 | (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); |
| 699 | printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); |
| 700 | printf ("IRQs:\n"); |
| 701 | printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); |
| 702 | printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); |
| 703 | printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); |
| 704 | printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); |
| 705 | printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); |
| 706 | printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); |
| 707 | } |
| 708 | |
| 709 | |