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Srinath915162d2011-04-18 17:40:35 -04001/*
2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
3 *
4 * Author: Srinath.R <srinath@mistralsolutions.com>
5 *
6 * Based on include/configs/am3517evm.h
7 *
8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Srinath915162d2011-04-18 17:40:35 -040011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
Srinath915162d2011-04-18 17:40:35 -040019#define CONFIG_OMAP 1 /* in a TI OMAP core */
20#define CONFIG_OMAP34XX 1 /* which is a 34XX */
21#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
Lokesh Vutla806d2792013-07-30 11:36:30 +053022#define CONFIG_OMAP_COMMON
Srinath915162d2011-04-18 17:40:35 -040023
24#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
25
26#include <asm/arch/cpu.h> /* get chip and board defs */
27#include <asm/arch/omap3.h>
28
29/*
30 * Display CPU and Board information
31 */
32#define CONFIG_DISPLAY_CPUINFO 1
33#define CONFIG_DISPLAY_BOARDINFO 1
34
35/* Clock Defines */
36#define V_OSCK 26000000 /* Clock output from T2 */
37#define V_SCLK (V_OSCK >> 1)
38
Srinath915162d2011-04-18 17:40:35 -040039#define CONFIG_MISC_INIT_R
40
41#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42#define CONFIG_SETUP_MEMORY_TAGS 1
43#define CONFIG_INITRD_TAG 1
44#define CONFIG_REVISION_TAG 1
45
46/*
47 * Size of malloc() pool
48 */
49#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
50#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
51 /* initial data */
52/*
53 * DDR related
54 */
Srinath915162d2011-04-18 17:40:35 -040055#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
56
57/*
58 * Hardware drivers
59 */
60
61/*
62 * NS16550 Configuration
63 */
64#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
65
66#define CONFIG_SYS_NS16550
67#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE (-4)
69#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
70
71/*
72 * select serial console configuration
73 */
74#define CONFIG_CONS_INDEX 3
75#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
76#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
77
78/* allow to overwrite serial and ethaddr */
79#define CONFIG_ENV_OVERWRITE
80#define CONFIG_BAUDRATE 115200
81#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 115200}
Tom Rinia5a88212011-09-03 21:51:50 -040083#define CONFIG_GENERIC_MMC 1
Srinath915162d2011-04-18 17:40:35 -040084#define CONFIG_MMC 1
Tom Rinia5a88212011-09-03 21:51:50 -040085#define CONFIG_OMAP_HSMMC 1
Srinath915162d2011-04-18 17:40:35 -040086#define CONFIG_DOS_PARTITION 1
87
88/*
89 * USB configuration
90 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
91 * Enable CONFIG_MUSB_UDC for Device functionalities.
92 */
93#define CONFIG_USB_AM35X 1
94#define CONFIG_MUSB_HCD 1
95
96#ifdef CONFIG_USB_AM35X
97
98#ifdef CONFIG_MUSB_HCD
99#define CONFIG_CMD_USB
100
101#define CONFIG_USB_STORAGE
102#define CONGIG_CMD_STORAGE
103#define CONFIG_CMD_FAT
104
105#ifdef CONFIG_USB_KEYBOARD
106#define CONFIG_SYS_USB_EVENT_POLL
107#define CONFIG_PREBOOT "usb start"
108#endif /* CONFIG_USB_KEYBOARD */
109
110#endif /* CONFIG_MUSB_HCD */
111
112#ifdef CONFIG_MUSB_UDC
113/* USB device configuration */
114#define CONFIG_USB_DEVICE 1
115#define CONFIG_USB_TTY 1
116#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
117/* Change these to suit your needs */
118#define CONFIG_USBD_VENDORID 0x0451
119#define CONFIG_USBD_PRODUCTID 0x5678
120#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
121#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
122#endif /* CONFIG_MUSB_UDC */
123
124#endif /* CONFIG_USB_AM35X */
125
126/* commands to include */
127#include <config_cmd_default.h>
128
129#define CONFIG_CMD_EXT2 /* EXT2 Support */
130#define CONFIG_CMD_FAT /* FAT support */
131#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
132
133#define CONFIG_CMD_I2C /* I2C serial bus support */
134#define CONFIG_CMD_MMC /* MMC support */
135#define CONFIG_CMD_NAND /* NAND support */
136#define CONFIG_CMD_DHCP
Joe Hershberger80615002012-05-23 07:57:57 +0000137#undef CONFIG_CMD_PING
Srinath915162d2011-04-18 17:40:35 -0400138
139#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
140#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
141#undef CONFIG_CMD_IMI /* iminfo */
142#undef CONFIG_CMD_IMLS /* List all found images */
143
144#define CONFIG_SYS_NO_FLASH
Heiko Schocher6789e842013-10-22 11:03:18 +0200145#define CONFIG_SYS_I2C
146#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
147#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
148#define CONFIG_SYS_I2C_OMAP34XX
Srinath915162d2011-04-18 17:40:35 -0400149
150#undef CONFIG_CMD_NET
151#undef CONFIG_CMD_NFS
152/*
153 * Board NAND Info.
154 */
155#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
156 /* to access nand */
157#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
158 /* to access */
159 /* nand at CS0 */
160
161#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
162 /* NAND devices */
Srinath915162d2011-04-18 17:40:35 -0400163
164#define CONFIG_JFFS2_NAND
165/* nand device jffs2 lives on */
166#define CONFIG_JFFS2_DEV "nand0"
167/* start of jffs2 partition */
168#define CONFIG_JFFS2_PART_OFFSET 0x680000
169#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
170
171/* Environment information */
172#define CONFIG_BOOTDELAY 10
173
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000174#define CONFIG_BOOTFILE "uImage"
Srinath915162d2011-04-18 17:40:35 -0400175
176#define CONFIG_EXTRA_ENV_SETTINGS \
177 "loadaddr=0x82000000\0" \
178 "console=ttyS2,115200n8\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400179 "mmcdev=0\0" \
Srinath915162d2011-04-18 17:40:35 -0400180 "mmcargs=setenv bootargs console=${console} " \
181 "root=/dev/mmcblk0p2 rw " \
182 "rootfstype=ext3 rootwait\0" \
183 "nandargs=setenv bootargs console=${console} " \
184 "root=/dev/mtdblock4 rw " \
185 "rootfstype=jffs2\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400186 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
Srinath915162d2011-04-18 17:40:35 -0400187 "bootscript=echo Running bootscript from mmc ...; " \
188 "source ${loadaddr}\0" \
Tom Rinia5a88212011-09-03 21:51:50 -0400189 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
Srinath915162d2011-04-18 17:40:35 -0400190 "mmcboot=echo Booting from mmc ...; " \
191 "run mmcargs; " \
192 "bootm ${loadaddr}\0" \
193 "nandboot=echo Booting from nand ...; " \
194 "run nandargs; " \
195 "nand read ${loadaddr} 280000 400000; " \
196 "bootm ${loadaddr}\0" \
197
198#define CONFIG_BOOTCOMMAND \
Andrew Bradford66968112012-10-01 05:06:52 +0000199 "mmc dev ${mmcdev}; if mmc rescan; then " \
Srinath915162d2011-04-18 17:40:35 -0400200 "if run loadbootscript; then " \
201 "run bootscript; " \
202 "else " \
203 "if run loaduimage; then " \
204 "run mmcboot; " \
205 "else run nandboot; " \
206 "fi; " \
207 "fi; " \
208 "else run nandboot; fi"
209
210#define CONFIG_AUTO_COMPLETE 1
211/*
212 * Miscellaneous configurable options
213 */
214#define V_PROMPT "AM3517_CRANE # "
215
216#define CONFIG_SYS_LONGHELP /* undef to save memory */
217#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Srinath915162d2011-04-18 17:40:35 -0400218#define CONFIG_SYS_PROMPT V_PROMPT
219#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
220/* Print Buffer Size */
221#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
222 sizeof(CONFIG_SYS_PROMPT) + 16)
223#define CONFIG_SYS_MAXARGS 32 /* max number of command */
224 /* args */
225/* Boot Argument Buffer Size */
226#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
227/* memtest works on */
228#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
229#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
230 0x01F00000) /* 31MB */
231
232#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
233 /* address */
234
235/*
236 * AM3517 has 12 GP timers, they can be driven by the system clock
237 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
238 * This rate is divided by a local divisor.
239 */
240#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
241#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Srinath915162d2011-04-18 17:40:35 -0400242
243/*-----------------------------------------------------------------------
Srinath915162d2011-04-18 17:40:35 -0400244 * Physical Memory Map
245 */
246#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
247#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Srinath915162d2011-04-18 17:40:35 -0400248#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
249
Srinath915162d2011-04-18 17:40:35 -0400250/*-----------------------------------------------------------------------
251 * FLASH and environment organization
252 */
253
254/* **** PISMO SUPPORT *** */
255
256/* Configure the PISMO */
257#define PISMO1_NAND_SIZE GPMC_SIZE_128M
258#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
259
260#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
261 /* on one chip */
262#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
263#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
264
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400265#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
Srinath915162d2011-04-18 17:40:35 -0400266
267/* Monitor at start of flash */
268#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
269
270#define CONFIG_NAND_OMAP_GPMC
271#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
272#define CONFIG_ENV_IS_IN_NAND 1
273#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
274
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400275#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
276#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
277#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
Srinath915162d2011-04-18 17:40:35 -0400278
279/*-----------------------------------------------------------------------
280 * CFI FLASH driver setup
281 */
282/* timeout values are in ticks */
283#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
284#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
285
286/* Flash banks JFFS2 should use */
287#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
288 CONFIG_SYS_MAX_NAND_DEVICE)
289#define CONFIG_SYS_JFFS2_MEM_NAND
290/* use flash_info[2] */
291#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
292#define CONFIG_SYS_JFFS2_NUM_BANKS 1
293
Srinath915162d2011-04-18 17:40:35 -0400294#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
295#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
296#define CONFIG_SYS_INIT_RAM_SIZE 0x800
297#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
298 CONFIG_SYS_INIT_RAM_SIZE - \
299 GENERATED_GBL_DATA_SIZE)
Tom Rinid067cc42011-11-18 12:48:11 +0000300
301/* Defines for SPL */
302#define CONFIG_SPL
Tom Rini47f7bca2012-08-13 12:03:19 -0700303#define CONFIG_SPL_FRAMEWORK
Tom Rinid7cb93b2012-08-14 12:26:08 -0700304#define CONFIG_SPL_BOARD_INIT
Tom Rinid067cc42011-11-18 12:48:11 +0000305#define CONFIG_SPL_NAND_SIMPLE
306#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinie0820cc2012-05-08 07:29:31 +0000307#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Tom Rinid067cc42011-11-18 12:48:11 +0000308#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
309
310#define CONFIG_SPL_BSS_START_ADDR 0x80000000
311#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
312
313#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
314#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
315#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
316#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
317
318#define CONFIG_SPL_LIBCOMMON_SUPPORT
319#define CONFIG_SPL_LIBDISK_SUPPORT
320#define CONFIG_SPL_I2C_SUPPORT
321#define CONFIG_SPL_LIBGENERIC_SUPPORT
322#define CONFIG_SPL_MMC_SUPPORT
323#define CONFIG_SPL_FAT_SUPPORT
324#define CONFIG_SPL_SERIAL_SUPPORT
325#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500326#define CONFIG_SPL_NAND_BASE
327#define CONFIG_SPL_NAND_DRIVERS
328#define CONFIG_SPL_NAND_ECC
Tom Rinid067cc42011-11-18 12:48:11 +0000329#define CONFIG_SPL_POWER_SUPPORT
330#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
331
332/* NAND boot config */
333#define CONFIG_SYS_NAND_5_ADDR_CYCLE
334#define CONFIG_SYS_NAND_PAGE_COUNT 64
335#define CONFIG_SYS_NAND_PAGE_SIZE 2048
336#define CONFIG_SYS_NAND_OOBSIZE 64
337#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
338#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
339#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
340 10, 11, 12, 13}
341#define CONFIG_SYS_NAND_ECCSIZE 512
342#define CONFIG_SYS_NAND_ECCBYTES 3
pekon gupta3f719062013-11-18 19:03:01 +0530343#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
Tom Rinid067cc42011-11-18 12:48:11 +0000344#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
345#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
346
347/*
348 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
349 * 64 bytes before this address should be set aside for u-boot.img's
350 * header. That is 0x800FFFC0--0x80100000 should not be used for any
351 * other needs.
352 */
353#define CONFIG_SYS_TEXT_BASE 0x80100000
354#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
355#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
356
Srinath915162d2011-04-18 17:40:35 -0400357#endif /* __CONFIG_H */