blob: 46d91e22de988ea45b8e8ed6a431f8b56acc8766 [file] [log] [blame]
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07001/**
2 * (C) Copyright 2014, Cavium Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5**/
6
7#ifndef __THUNDERX_88XX_H__
8#define __THUNDERX_88XX_H__
9
10#define CONFIG_REMAKE_ELF
11
12#define CONFIG_THUNDERX
13
14#define CONFIG_SYS_64BIT
15
16#define CONFIG_SYS_NO_FLASH
17
18
19#define CONFIG_IDENT_STRING \
20 " for Cavium Thunder CN88XX ARM v8 Multi-Core"
21#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
22
23#define MEM_BASE 0x00500000
24
Sergey Temerkhanov900f88f2015-10-14 09:55:51 -070025#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
26
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070027/* Link Definitions */
28#define CONFIG_SYS_TEXT_BASE 0x00500000
29#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
30
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070031/* SMP Spin Table Definitions */
32#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
33
34
35/* Generic Timer Definitions */
36#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
37
38
39#define CONFIG_SYS_MEMTEST_START MEM_BASE
40#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
41
42/* Size of malloc() pool */
43#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
44
45/* PL011 Serial Configuration */
46
47#define CONFIG_PL01X_SERIAL
48#define CONFIG_PL011_CLOCK 24000000
49#define CONFIG_CONS_INDEX 1
50
51/* Generic Interrupt Controller Definitions */
52#define GICD_BASE (0x801000000000)
53#define GICR_BASE (0x801000002000)
54#define CONFIG_SYS_SERIAL0 0x87e024000000
55#define CONFIG_SYS_SERIAL1 0x87e025000000
56
57#define CONFIG_BAUDRATE 115200
58
59/* Command line configuration */
60#define CONFIG_MENU
61
62/* BOOTP options */
63#define CONFIG_BOOTP_BOOTFILESIZE
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_GATEWAY
66#define CONFIG_BOOTP_HOSTNAME
67#define CONFIG_BOOTP_PXE
68#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
69
70/* Miscellaneous configurable options */
71#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
72
73/* Physical Memory Map */
74#define CONFIG_NR_DRAM_BANKS 1
75#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
76#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
77#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
78
79/* Initial environment variables */
80#define UBOOT_IMG_HEAD_SIZE 0x40
81/* C80000 - 0x40 */
82#define CONFIG_EXTRA_ENV_SETTINGS \
83 "kernel_addr=08007ffc0\0" \
84 "fdt_addr=0x94C00000\0" \
85 "fdt_high=0x9fffffff\0"
86
87#define CONFIG_BOOTARGS \
88 "console=ttyAMA0,115200n8 " \
89 "earlycon=pl011,0x87e024000000 " \
90 "debug maxcpus=48 rootwait rw "\
91 "root=/dev/sda2 coherent_pool=16M"
92#define CONFIG_BOOTDELAY 5
93
94/* Do not preserve environment */
95#define CONFIG_ENV_IS_NOWHERE 1
96#define CONFIG_ENV_SIZE 0x1000
97
98/* Monitor Command Prompt */
99#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
100#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
101 sizeof(CONFIG_SYS_PROMPT) + 16)
102#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
104#define CONFIG_SYS_LONGHELP
105#define CONFIG_CMDLINE_EDITING 1
106#define CONFIG_SYS_MAXARGS 64 /* max command args */
107#define CONFIG_NO_RELOCATION 1
108#define CONFIG_LIB_RAND
109#define PLL_REF_CLK 50000000 /* 50 MHz */
110#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
111
112#endif /* __THUNDERX_88XX_H__ */