blob: 15f8f3163d7fac3ed0a0577bd1d2273bda7245be [file] [log] [blame]
Anatolij Gustschina3921ee2010-04-24 19:27:09 +02001/*
2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
3 *
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschina3921ee2010-04-24 19:27:09 +02008 */
9
10#include <common.h>
11#include <asm/bitops.h>
12#include <command.h>
13#include <asm/io.h>
14#include <asm/processor.h>
15#include <asm/mpc512x.h>
16#include <fdt_support.h>
17#include <flash.h>
18#ifdef CONFIG_MISC_INIT_R
19#include <i2c.h>
20#endif
21#include <serial.h>
22#include <jffs2/load_kernel.h>
23#include <mtd_node.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27extern flash_info_t flash_info[];
28ulong flash_get_size (phys_addr_t base, int banknum);
29
Anatolij Gustschina3921ee2010-04-24 19:27:09 +020030sdram_conf_t mddrc_config[] = {
31 {
32 (512 << 20), /* 512 MB RAM configuration */
33 {
34 CONFIG_SYS_MDDRC_SYS_CFG,
35 CONFIG_SYS_MDDRC_TIME_CFG0,
36 CONFIG_SYS_MDDRC_TIME_CFG1,
37 CONFIG_SYS_MDDRC_TIME_CFG2
38 }
39 },
40 {
41 (128 << 20), /* 128 MB RAM configuration */
42 {
43 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
44 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
45 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
46 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
47 }
48 },
49};
50
51phys_size_t initdram (int board_type)
52{
53 int i;
54 u32 msize = 0;
55 u32 pdm360ng_init_seq[] = {
56 CONFIG_SYS_DDRCMD_NOP,
57 CONFIG_SYS_DDRCMD_NOP,
58 CONFIG_SYS_DDRCMD_NOP,
59 CONFIG_SYS_DDRCMD_NOP,
60 CONFIG_SYS_DDRCMD_NOP,
61 CONFIG_SYS_DDRCMD_NOP,
62 CONFIG_SYS_DDRCMD_NOP,
63 CONFIG_SYS_DDRCMD_NOP,
64 CONFIG_SYS_DDRCMD_NOP,
65 CONFIG_SYS_DDRCMD_NOP,
66 CONFIG_SYS_DDRCMD_PCHG_ALL,
67 CONFIG_SYS_DDRCMD_NOP,
68 CONFIG_SYS_DDRCMD_RFSH,
69 CONFIG_SYS_DDRCMD_NOP,
70 CONFIG_SYS_DDRCMD_RFSH,
71 CONFIG_SYS_DDRCMD_NOP,
72 CONFIG_SYS_MICRON_INIT_DEV_OP,
73 CONFIG_SYS_DDRCMD_NOP,
74 CONFIG_SYS_DDRCMD_EM2,
75 CONFIG_SYS_DDRCMD_NOP,
76 CONFIG_SYS_DDRCMD_PCHG_ALL,
77 CONFIG_SYS_DDRCMD_EM2,
78 CONFIG_SYS_DDRCMD_EM3,
79 CONFIG_SYS_DDRCMD_EN_DLL,
80 CONFIG_SYS_DDRCMD_RES_DLL,
81 CONFIG_SYS_DDRCMD_PCHG_ALL,
82 CONFIG_SYS_DDRCMD_RFSH,
83 CONFIG_SYS_DDRCMD_RFSH,
84 CONFIG_SYS_MICRON_INIT_DEV_OP,
85 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
86 CONFIG_SYS_DDRCMD_OCD_EXIT,
87 CONFIG_SYS_DDRCMD_PCHG_ALL,
88 CONFIG_SYS_DDRCMD_NOP
89 };
90
91 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
92 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
93 ARRAY_SIZE(pdm360ng_init_seq));
94 if (msize == mddrc_config[i].size)
95 break;
96 }
97
98 return msize;
99}
100
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200101static int set_lcd_brightness(char *);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200102
103int misc_init_r(void)
104{
105 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
106
107 /*
108 * Re-configure flash setup using auto-detected info
109 */
110 if (flash_info[1].size > 0) {
111 out_be32(&im->sysconf.lpcs1aw,
112 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
113 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
114 flash_info[1].size));
115 sync_law(&im->sysconf.lpcs1aw);
116 /*
117 * Re-check to get correct base address
118 */
119 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
120 } else {
121 /* Disable Bank 1 */
122 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
123 sync_law(&im->sysconf.lpcs1aw);
124 }
125
126 out_be32(&im->sysconf.lpcs0aw,
127 CSAW_START(gd->bd->bi_flashstart) |
128 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
129 sync_law(&im->sysconf.lpcs0aw);
130
131 /*
132 * Re-check to get correct base address
133 */
134 flash_get_size (gd->bd->bi_flashstart, 0);
135
136 /*
137 * Re-do flash protection upon new addresses
138 */
139 flash_protect (FLAG_PROTECT_CLEAR,
140 gd->bd->bi_flashstart, 0xffffffff,
141 &flash_info[0]);
142
143 /* Monitor protection ON by default */
144 flash_protect (FLAG_PROTECT_SET,
145 CONFIG_SYS_MONITOR_BASE,
146 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
147 &flash_info[0]);
148
149 /* Environment protection ON by default */
150 flash_protect (FLAG_PROTECT_SET,
151 CONFIG_ENV_ADDR,
152 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
153 &flash_info[0]);
154
155#ifdef CONFIG_ENV_ADDR_REDUND
156 /* Redundant environment protection ON by default */
157 flash_protect (FLAG_PROTECT_SET,
158 CONFIG_ENV_ADDR_REDUND,
159 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
160 &flash_info[0]);
161#endif
162
163#ifdef CONFIG_FSL_DIU_FB
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200164 set_lcd_brightness(0);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200165 /* Switch LCD-Backlight and LVDS-Interface on */
166 setbits_be32(&im->gpio.gpdir, 0x01040000);
167 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
168#endif
169
170#if defined(CONFIG_HARD_I2C)
171 if (!getenv("ethaddr")) {
172 uchar buf[6];
173 uchar ifm_oui[3] = { 0, 2, 1, };
174 int ret;
175
176 /* I2C-0 for on-board eeprom */
177 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
178
179 /* Read ethaddr from EEPROM */
180 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
181 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
182 if (ret != 0) {
183 printf("Error: Unable to read MAC from I2C"
184 " EEPROM at address %02X:%02X\n",
185 CONFIG_SYS_I2C_EEPROM_ADDR,
186 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
187 return 1;
188 }
189
190 /* Owned by IFM ? */
191 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
192 printf("Illegal MAC address in EEPROM: %pM\n", buf);
193 return 1;
194 }
195
196 eth_setenv_enetaddr("ethaddr", buf);
197 }
198#endif /* defined(CONFIG_HARD_I2C) */
199
200 return 0;
201}
202
203static iopin_t ioregs_init[] = {
204 /* FUNC1=LPC_CS4 */
205 {
206 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
207 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
208 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
209 },
210 /* FUNC3=GPIO10 */
211 {
212 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
213 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
214 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
215 },
216 /* FUNC1=CAN3_TX */
217 {
218 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
219 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
220 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
221 },
222 /* FUNC3=GPIO14 */
223 {
224 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
225 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
226 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
227 },
228 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
229 /* DIU_LD22-DIU_LD23 */
230 {
231 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
232 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
233 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
234 },
235 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
236 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
237 {
238 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
239 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
240 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
241 },
242 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
243 /* VIU_DATA0-VIU_DATA2 */
244 {
245 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
246 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
247 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
248 },
249 /* FUNC2=FEC_TXD_0 */
250 {
251 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
252 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
253 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
254 },
255 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
256 /* VIU_DATA3, VIU_DATA4 */
257 {
258 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
259 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
260 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
261 },
262 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
263 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
264 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
265 {
266 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
267 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
268 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
269 },
270 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
271 /* DIU_LD00-DIU_LD21 */
272 {
273 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
274 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
275 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
276 },
277 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
278 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
279 {
280 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
281 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
282 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
283 },
284 /* FUNC2=CAN3_RX */
285 {
286 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
287 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
288 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
289 },
290 /* Sets lowest slew on 2 CAN_TX Pins*/
291 {
292 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
293 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
294 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
295 },
296 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
297 /* CAN4_TX, CAN4_RX */
298 {
299 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
300 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
301 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
302 },
303 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
304 /* GPIO8, GPIO9 */
305 {
306 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
307 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
308 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
309 },
310 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
311 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
312 {
313 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
314 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
315 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
316 },
317 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
318 /* FEC_RXD_3, FEC_RXD_2 */
319 {
320 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
321 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
322 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
323 },
324 /* FUNC3=GPIO17 */
325 {
326 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
327 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
328 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
329 },
330 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
331 /* GPIO2, GPIO20, GPIO21 */
332 {
333 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
334 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
335 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
336 },
337 /* FUNC2=VIU_PIX_CLK */
338 {
339 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
340 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
341 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
342 },
343 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
344 /* GPIO24, GPIO25 */
345 {
346 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
347 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
348 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
349 },
350 /* FUNC1=NFC_CE2 */
351 {
352 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
353 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
354 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
355 },
356 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
357 /* VIU_DATA5-VIU_DATA9 */
358 {
359 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
360 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
361 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
362 },
363 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
364 /* LPC_TSIZ1-LPC_TSIZ2 */
365 {
366 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
367 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
368 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
369 },
370 /* FUNC1=LPC_TS */
371 {
372 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
373 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
374 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
375 },
376 /* FUNC3=GPIO16 */
377 {
378 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
379 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
380 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
381 },
382 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
383 /* GPIO18-GPIO19, GPT7/GPIO7 */
384 {
385 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
386 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
387 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
388 },
389 /* FUNC3=GPIO0/GPT0 */
390 {
391 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
392 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
393 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
394 },
395 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
396 /* GPIO11, GPIO2, GPIO12, GPIO13 */
397 {
398 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
399 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
400 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
401 },
402 /* FUNC2=DIU_DE */
403 {
404 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
405 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
406 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
407 }
408};
409
410int checkboard (void)
411{
412 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
413
414 puts("Board: PDM360NG\n");
415
416 /* initialize function mux & slew rate IO inter alia on IO Pins */
417
418 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
419
420 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
421 setbits_be32(&im->io_ctrl.io_control_gp,
422 (1 << 0) | /* GP_MUX7->GPIO7 */
423 (1 << 5)); /* GP_MUX2->GPIO2 */
424
425 /* configure GPIO24 (VIU_CE), output/high */
426 setbits_be32(&im->gpio.gpdir, 0x80);
427 setbits_be32(&im->gpio.gpdat, 0x80);
428
429 return 0;
430}
431
432#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
433#ifdef CONFIG_FDT_FIXUP_PARTITIONS
434struct node_info nodes[] = {
435 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
436 { "cfi-flash", MTD_DEV_TYPE_NOR, },
437};
438#endif
439
Anatolij Gustschin6213b8f2010-08-17 17:46:02 +0200440#if defined(CONFIG_VIDEO)
441/*
442 * EDID block has been generated using Phoenix EDID Designer 1.3.
443 * This tool creates a text file containing:
444 *
445 * EDID BYTES:
446 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
447 * ------------------------------------------------
448 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
449 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
450 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
451 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
452 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
453 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
454 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
455 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
456 *
457 * Then this data has been manually converted to the char
458 * array below.
459 */
460static unsigned char edid_buf[128] = {
461 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
462 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
463 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
464 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
465 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
466 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
467 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
468 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
469 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
470 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
471 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
472 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
473 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
474 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
475 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
476 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
477};
478#endif
479
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200480void ft_board_setup(void *blob, bd_t *bd)
481{
482 u32 val[8];
483 int rc, i = 0;
484
485 ft_cpu_setup(blob, bd);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200486#ifdef CONFIG_FDT_FIXUP_PARTITIONS
487 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
488#endif
Anatolij Gustschin6213b8f2010-08-17 17:46:02 +0200489#if defined(CONFIG_VIDEO)
490 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
491#endif
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200492
493 /* Fixup NOR FLASH mapping */
494 val[i++] = 0; /* chip select number */
495 val[i++] = 0; /* always 0 */
496 val[i++] = gd->bd->bi_flashstart;
497 val[i++] = gd->bd->bi_flashsize;
498
499 /* Fixup MRAM mapping */
500 val[i++] = 2; /* chip select number */
501 val[i++] = 0; /* always 0 */
502 val[i++] = CONFIG_SYS_MRAM_BASE;
503 val[i++] = CONFIG_SYS_MRAM_SIZE;
504
505 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
506 val, i * sizeof(u32), 1);
507 if (rc)
508 printf("Unable to update localbus ranges, err=%s\n",
509 fdt_strerror(rc));
510
511 /* Fixup reg property in NOR Flash node */
512 i = 0;
513 val[i++] = 0; /* always 0 */
514 val[i++] = 0; /* start at offset 0 */
515 val[i++] = flash_info[0].size; /* size of Bank 0 */
516
517 /* Second Bank available? */
518 if (flash_info[1].size > 0) {
519 val[i++] = 0; /* always 0 */
520 val[i++] = flash_info[0].size; /* offset of Bank 1 */
521 val[i++] = flash_info[1].size; /* size of Bank 1 */
522 }
523
524 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
525 val, i * sizeof(u32), 1);
526 if (rc)
527 printf("Unable to update flash reg property, err=%s\n",
528 fdt_strerror(rc));
529}
530#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
531
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200532/*
533 * If argument is NULL, set the LCD brightness to the
534 * value from "brightness" environment variable. Set
535 * the LCD brightness to the value specified by the
536 * argument otherwise. Default brightness is zero.
537 */
538#define MAX_BRIGHTNESS 99
539static int set_lcd_brightness(char *brightness)
540{
541 struct stdio_dev *cop_port;
542 char *env;
543 char cmd_buf[20];
544 int val = 0;
545 int cs = 0;
546 int len, i;
547
548 if (brightness) {
549 val = simple_strtol(brightness, NULL, 10);
550 } else {
551 env = getenv("brightness");
552 if (env)
553 val = simple_strtol(env, NULL, 10);
554 }
555
556 if (val < 0)
557 val = 0;
558
559 if (val > MAX_BRIGHTNESS)
560 val = MAX_BRIGHTNESS;
561
562 sprintf(cmd_buf, "$SB;%04d;", val);
563
564 len = strlen(cmd_buf);
565 for (i = 1; i <= len; i++)
566 cs += cmd_buf[i];
567
568 cs = (~cs + 1) & 0xff;
569 sprintf(cmd_buf + len, "%02X\n", cs);
570
571 /* IO Coprocessor communication */
572 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
573 if (!cop_port) {
574 printf("Error: Can't open IO Coprocessor port.\n");
575 return -1;
576 }
577
578 debug("%s: cmd: %s", __func__, cmd_buf);
579 write_port(cop_port, cmd_buf);
580 /*
581 * Wait for transmission and maybe response data
582 * before closing the port.
583 */
584 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
585 memset(cmd_buf, 0, sizeof(cmd_buf));
586 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
587 if (len)
588 printf("Error: %s\n", cmd_buf);
589
590 close_port(4);
591
592 return 0;
593}
594
595static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200596 int argc, char * const argv[])
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200597{
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200598 if (argc < 2)
599 return cmd_usage(cmdtp);
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200600
601 return set_lcd_brightness(argv[1]);
602}
603
604U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
605 "set LCD brightness",
606 "<brightness> - set LCD backlight level to <brightness>.\n"
607);