blob: 027755de8487fa6a6e3a07431ffbb1c11670a04b [file] [log] [blame]
Chander Kashyape21185b2011-05-24 20:02:56 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Chander Kashyape21185b2011-05-24 20:02:56 +00005 */
6
7#include <common.h>
Simon Glass903fd792014-10-20 19:48:37 -06008#include <asm/gpio.h>
Chander Kashyape21185b2011-05-24 20:02:56 +00009#include <asm/io.h>
10#include <netdev.h>
11#include <asm/arch/cpu.h>
Chander Kashyape21185b2011-05-24 20:02:56 +000012#include <asm/arch/mmc.h>
Rajeshwari Shinde198a40b2013-07-04 12:29:16 +053013#include <asm/arch/periph.h>
14#include <asm/arch/pinmux.h>
Chander Kashyape21185b2011-05-24 20:02:56 +000015#include <asm/arch/sromc.h>
16
17DECLARE_GLOBAL_DATA_PTR;
Chander Kashyape21185b2011-05-24 20:02:56 +000018
19static void smc9115_pre_init(void)
20{
21 u32 smc_bw_conf, smc_bc_conf;
22
23 /* gpio configuration GPK0CON */
Akshay Saraswatf6ae1ca2014-05-13 10:30:14 +053024 gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
Chander Kashyape21185b2011-05-24 20:02:56 +000025
26 /* Ethernet needs bus width of 16 bits */
27 smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
28 smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
29 | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
30 | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
31 | SROMC_BC_PMC(0x0F);
32
33 /* Select and configure the SROMC bank */
34 s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
35}
36
37int board_init(void)
38{
Chander Kashyape21185b2011-05-24 20:02:56 +000039 smc9115_pre_init();
40
Chander Kashyape21185b2011-05-24 20:02:56 +000041 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
42 return 0;
43}
44
45int dram_init(void)
46{
47 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
48 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
49 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
50 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
51
52 return 0;
53}
54
Simon Glass76b00ac2017-03-31 08:40:32 -060055int dram_init_banksize(void)
Chander Kashyape21185b2011-05-24 20:02:56 +000056{
57 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Minkyu Kang6b949ba2015-10-23 15:59:37 +090058 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
Chander Kashyap9436a0c2011-09-20 21:25:02 +000059 PHYS_SDRAM_1_SIZE);
Chander Kashyape21185b2011-05-24 20:02:56 +000060 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Minkyu Kang6b949ba2015-10-23 15:59:37 +090061 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
Chander Kashyap9436a0c2011-09-20 21:25:02 +000062 PHYS_SDRAM_2_SIZE);
Chander Kashyape21185b2011-05-24 20:02:56 +000063 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
Minkyu Kang6b949ba2015-10-23 15:59:37 +090064 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
Chander Kashyap9436a0c2011-09-20 21:25:02 +000065 PHYS_SDRAM_3_SIZE);
Chander Kashyape21185b2011-05-24 20:02:56 +000066 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
Minkyu Kang6b949ba2015-10-23 15:59:37 +090067 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
Chander Kashyap9436a0c2011-09-20 21:25:02 +000068 PHYS_SDRAM_4_SIZE);
Simon Glass76b00ac2017-03-31 08:40:32 -060069
70 return 0;
Chander Kashyape21185b2011-05-24 20:02:56 +000071}
72
73int board_eth_init(bd_t *bis)
74{
75 int rc = 0;
76#ifdef CONFIG_SMC911X
77 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
78#endif
79 return rc;
80}
81
82#ifdef CONFIG_DISPLAY_BOARDINFO
83int checkboard(void)
84{
85 printf("\nBoard: SMDKV310\n");
86 return 0;
87}
88#endif
89
Masahiro Yamada4aa2ba32017-05-09 20:31:39 +090090#ifdef CONFIG_MMC
Chander Kashyape21185b2011-05-24 20:02:56 +000091int board_mmc_init(bd_t *bis)
92{
93 int i, err;
94
95 /*
96 * MMC2 SD card GPIO:
97 *
98 * GPK2[0] SD_2_CLK(2)
99 * GPK2[1] SD_2_CMD(2)
100 * GPK2[2] SD_2_CDn
101 * GPK2[3:6] SD_2_DATA[0:3](2)
102 */
Akshay Saraswatf6ae1ca2014-05-13 10:30:14 +0530103 for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
Chander Kashyape21185b2011-05-24 20:02:56 +0000104 /* GPK2[0:6] special function 2 */
Akshay Saraswatf6ae1ca2014-05-13 10:30:14 +0530105 gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
Chander Kashyape21185b2011-05-24 20:02:56 +0000106
107 /* GPK2[0:6] drv 4x */
Akshay Saraswatf6ae1ca2014-05-13 10:30:14 +0530108 gpio_set_drv(i, S5P_GPIO_DRV_4X);
Chander Kashyape21185b2011-05-24 20:02:56 +0000109
110 /* GPK2[0:1] pull disable */
Akshay Saraswatf6ae1ca2014-05-13 10:30:14 +0530111 if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
112 gpio_set_pull(i, S5P_GPIO_PULL_NONE);
Chander Kashyape21185b2011-05-24 20:02:56 +0000113 continue;
114 }
115
116 /* GPK2[2:6] pull up */
Akshay Saraswatf6ae1ca2014-05-13 10:30:14 +0530117 gpio_set_pull(i, S5P_GPIO_PULL_UP);
Chander Kashyape21185b2011-05-24 20:02:56 +0000118 }
119 err = s5p_mmc_init(2, 4);
120 return err;
121}
122#endif
Rajeshwari Shinde198a40b2013-07-04 12:29:16 +0530123
124static int board_uart_init(void)
125{
126 int err;
127
128 err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
129 if (err) {
130 debug("UART0 not configured\n");
131 return err;
132 }
133
134 err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
135 if (err) {
136 debug("UART1 not configured\n");
137 return err;
138 }
139
140 err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
141 if (err) {
142 debug("UART2 not configured\n");
143 return err;
144 }
145
146 err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
147 if (err) {
148 debug("UART3 not configured\n");
149 return err;
150 }
151
152 return 0;
153}
154
155#ifdef CONFIG_BOARD_EARLY_INIT_F
156int board_early_init_f(void)
157{
158 int err;
159 err = board_uart_init();
160 if (err) {
161 debug("UART init failed\n");
162 return err;
163 }
164 return err;
165}
166#endif