blob: 1801d9d7d588cb3fc0ae0ec0cbdc7979f5975ea2 [file] [log] [blame]
TsiChungLiew1552af72008-01-14 17:43:33 -06001/*
2 * Configuation settings for the Freescale MCF52277 EVB board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M52277EVB_H
31#define _M52277EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF5227x /* define processor family */
38#define CONFIG_M52277 /* define processor type */
39#define CONFIG_M52277EVB /* M52277EVB board */
40
TsiChungLiew1552af72008-01-14 17:43:33 -060041#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
TsiChung Liewa21d0c22008-10-21 15:37:02 +000043#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
TsiChungLiew1552af72008-01-14 17:43:33 -060045
46#undef CONFIG_WATCHDOG
47
48#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49
50/*
51 * BOOTP options
52 */
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
58/* Command line configuration */
59#include <config_cmd_default.h>
60
61#define CONFIG_CMD_CACHE
62#define CONFIG_CMD_DATE
63#define CONFIG_CMD_ELF
64#define CONFIG_CMD_FLASH
65#define CONFIG_CMD_I2C
66#define CONFIG_CMD_JFFS2
67#define CONFIG_CMD_LOADB
68#define CONFIG_CMD_LOADS
69#define CONFIG_CMD_MEMORY
70#define CONFIG_CMD_MISC
71#undef CONFIG_CMD_NET
72#define CONFIG_CMD_REGINFO
73#undef CONFIG_CMD_USB
74#undef CONFIG_CMD_BMP
TsiChung Liewa21d0c22008-10-21 15:37:02 +000075#define CONFIG_CMD_SPI
76#define CONFIG_CMD_SF
TsiChungLiew1552af72008-01-14 17:43:33 -060077
TsiChung Liewa21d0c22008-10-21 15:37:02 +000078#define CONFIG_HOSTNAME M52277EVB
79#define CONFIG_SYS_UBOOT_END 0x3FFFF
80#define CONFIG_SYS_LOAD_ADDR2 0x40010007
81#ifdef CONFIG_SYS_STMICRO_BOOT
82/* ST Micro serial flash */
TsiChungLiew1552af72008-01-14 17:43:33 -060083#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liewa21d0c22008-10-21 15:37:02 +000085 "loadaddr=0x40010000\0" \
86 "uboot=u-boot.bin\0" \
87 "load=loadb ${loadaddr} ${baudrate};" \
88 "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
TsiChungLiew1552af72008-01-14 17:43:33 -060089 "upd=run load; run prog\0" \
TsiChung Liewa21d0c22008-10-21 15:37:02 +000090 "prog=sf probe 0:2 10000 1;" \
91 "sf erase 0 30000;" \
92 "sf write ${loadaddr} 0 30000;" \
TsiChungLiew1552af72008-01-14 17:43:33 -060093 "save\0" \
94 ""
TsiChung Liewa21d0c22008-10-21 15:37:02 +000095#endif
96#ifdef CONFIG_SYS_SPANSION_BOOT
97#define CONFIG_EXTRA_ENV_SETTINGS \
98 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
99 "loadaddr=0x40010000\0" \
100 "uboot=u-boot.bin\0" \
101 "load=loadb ${loadaddr} ${baudrate}\0" \
102 "upd=run load; run prog\0" \
103 "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
104 " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
105 "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
106 MK_STR(CONFIG_SYS_UBOOT_END) ";" \
107 "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
108 " ${filesize}; save\0" \
109 "updsbf=run loadsbf; run progsbf\0" \
110 "loadsbf=loadb ${loadaddr} ${baudrate};" \
111 "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
112 "progsbf=sf probe 0:2 10000 1;" \
113 "sf erase 0 30000;" \
114 "sf write ${loadaddr} 0 30000;" \
115 ""
116#endif
TsiChungLiew1552af72008-01-14 17:43:33 -0600117
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000118#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
TsiChungLiew1552af72008-01-14 17:43:33 -0600119/* LCD */
120#ifdef CONFIG_CMD_BMP
121#define CONFIG_LCD
122#define CONFIG_SPLASH_SCREEN
123#define CONFIG_LCD_LOGO
124#define CONFIG_SHARP_LQ035Q7DH06
125#endif
126
127/* USB */
128#ifdef CONFIG_CMD_USB
129#define CONFIG_USB_EHCI
130#define CONFIG_USB_STORAGE
131#define CONFIG_DOS_PARTITION
132#define CONFIG_MAC_PARTITION
133#define CONFIG_ISO_PARTITION
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000134#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_USB_EHCI_CPU_INIT
TsiChungLiew1552af72008-01-14 17:43:33 -0600136#endif
137
138/* Realtime clock */
139#define CONFIG_MCFRTC
140#undef RTC_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
TsiChungLiew1552af72008-01-14 17:43:33 -0600142
143/* Timer */
144#define CONFIG_MCFTMR
145#undef CONFIG_MCFPIT
146
147/* I2c */
148#define CONFIG_FSL_I2C
149#define CONFIG_HARD_I2C /* I2C with hardware support */
150#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
152#define CONFIG_SYS_I2C_SLAVE 0x7F
153#define CONFIG_SYS_I2C_OFFSET 0x58000
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000154#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
155
156/* DSPI and Serial Flash */
TsiChung Liewee0a8462009-06-30 14:18:29 +0000157#define CONFIG_CF_SPI
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000158#define CONFIG_CF_DSPI
159#define CONFIG_HARD_SPI
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000160#define CONFIG_SYS_SBFHDR_SIZE 0x7
161#ifdef CONFIG_CMD_SPI
162# define CONFIG_SYS_DSPI_CS2
163# define CONFIG_SPI_FLASH
164# define CONFIG_SPI_FLASH_STMICRO
165
TsiChung Liewee0a8462009-06-30 14:18:29 +0000166# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
167 DSPI_CTAR_PCSSCK_1CLK | \
168 DSPI_CTAR_PASC(0) | \
169 DSPI_CTAR_PDT(0) | \
170 DSPI_CTAR_CSSCK(0) | \
171 DSPI_CTAR_ASC(0) | \
172 DSPI_CTAR_DT(1))
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000173#endif
TsiChungLiew1552af72008-01-14 17:43:33 -0600174
175/* Input, PCI, Flexbus, and VCO */
176#define CONFIG_EXTRA_CLOCK
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_INPUT_CLKSRC 16000000
TsiChungLiew1552af72008-01-14 17:43:33 -0600179
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000180#define CONFIG_PRAM 2048 /* 2048 KB */
TsiChungLiew1552af72008-01-14 17:43:33 -0600181
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000182#define CONFIG_SYS_PROMPT "-> "
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew1552af72008-01-14 17:43:33 -0600184
185#if defined(CONFIG_CMD_KGDB)
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000186#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew1552af72008-01-14 17:43:33 -0600187#else
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000188#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew1552af72008-01-14 17:43:33 -0600189#endif
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000190#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
191#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
192#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChungLiew1552af72008-01-14 17:43:33 -0600193
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000194#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
TsiChungLiew1552af72008-01-14 17:43:33 -0600195
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000196#define CONFIG_SYS_HZ 1000
TsiChungLiew1552af72008-01-14 17:43:33 -0600197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiew1552af72008-01-14 17:43:33 -0600199
200/*
201 * Low Level Configuration Settings
202 * (address mappings, register initial values, etc.)
203 * You should know what you are doing if you make changes here.
204 */
205
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000206/*
TsiChungLiew1552af72008-01-14 17:43:33 -0600207 * Definitions for initial stack pointer and data area (in DPRAM)
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000210#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
211#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000213#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
214#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
215#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
TsiChungLiew1552af72008-01-14 17:43:33 -0600216
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000217/*
TsiChungLiew1552af72008-01-14 17:43:33 -0600218 * Start addresses for the final memory configuration
219 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew1552af72008-01-14 17:43:33 -0600221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_SDRAM_BASE 0x40000000
223#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
224#define CONFIG_SYS_SDRAM_CFG1 0x43711630
225#define CONFIG_SYS_SDRAM_CFG2 0x56670000
226#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
227#define CONFIG_SYS_SDRAM_EMOD 0x81810000
228#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000229#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
TsiChungLiew1552af72008-01-14 17:43:33 -0600230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
232#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew1552af72008-01-14 17:43:33 -0600233
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000234#ifdef CONFIG_CF_SBF
235# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
236#else
237# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
238#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
240#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
241#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiew1552af72008-01-14 17:43:33 -0600242
243/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000245#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiew1552af72008-01-14 17:43:33 -0600246
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000247/*
248 * Configuration for environment
TsiChungLiew1552af72008-01-14 17:43:33 -0600249 * Environment is embedded in u-boot in the second sector of the flash
250 */
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000251#ifdef CONFIG_CF_SBF
252# define CONFIG_ENV_IS_IN_SPI_FLASH
253# define CONFIG_ENV_SPI_CS 2
254#else
255# define CONFIG_ENV_IS_IN_FLASH 1
256#endif
257#define CONFIG_ENV_OVERWRITE 1
TsiChungLiew1552af72008-01-14 17:43:33 -0600258
259/*-----------------------------------------------------------------------
260 * FLASH organization
261 */
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000262#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liewee0a8462009-06-30 14:18:29 +0000263# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000264# define CONFIG_ENV_OFFSET 0x30000
265# define CONFIG_ENV_SIZE 0x1000
266# define CONFIG_ENV_SECT_SIZE 0x10000
267#endif
268#ifdef CONFIG_SYS_SPANSION_BOOT
269# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
270# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
271# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
272# define CONFIG_ENV_SIZE 0x1000
273# define CONFIG_ENV_SECT_SIZE 0x8000
274#endif
TsiChungLiew1552af72008-01-14 17:43:33 -0600275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_FLASH_CFI
277#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200278# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liewbbf6bbf2009-06-11 12:50:05 +0000279# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
280# define CONFIG_FLASH_SPANSION_S29WS_N 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
282# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
283# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
284# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
285# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
286# define CONFIG_SYS_FLASH_CHECKSUM
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000287# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
TsiChungLiew1552af72008-01-14 17:43:33 -0600288#endif
289
290/*
291 * This is setting for JFFS2 support in u-boot.
292 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
293 */
294#ifdef CONFIG_CMD_JFFS2
295# define CONFIG_JFFS2_DEV "nor0"
296# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
TsiChungLiew1552af72008-01-14 17:43:33 -0600298#endif
299
300/*-----------------------------------------------------------------------
301 * Cache Configuration
302 */
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000303#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew1552af72008-01-14 17:43:33 -0600304
305/*-----------------------------------------------------------------------
306 * Memory bank definitions
307 */
308/*
309 * CS0 - NOR Flash
310 * CS1 - Available
311 * CS2 - Available
312 * CS3 - Available
313 * CS4 - Available
314 * CS5 - Available
315 */
316
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000317#ifdef CONFIG_CF_SBF
318#define CONFIG_SYS_CS0_BASE 0x04000000
319#define CONFIG_SYS_CS0_MASK 0x00FF0001
320#define CONFIG_SYS_CS0_CTRL 0x00001FA0
321#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_CS0_BASE 0x00000000
323#define CONFIG_SYS_CS0_MASK 0x00FF0001
324#define CONFIG_SYS_CS0_CTRL 0x00001FA0
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000325#endif
TsiChungLiew1552af72008-01-14 17:43:33 -0600326
327#endif /* _M52277EVB_H */