blob: 36e952e741341671cf2e7520b0650b86ce10d4fc [file] [log] [blame]
Ron Madrid5bb907a2009-01-22 15:05:24 -08001/*
2 * Copyright (C) Sheldon Instruments, Inc. 2008
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22/*
23 * simpc8313 board configuration file
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_NAND_U_BOOT
33
34#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050035#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050036#define CONFIG_MPC831x 1
Ron Madrid5bb907a2009-01-22 15:05:24 -080037#define CONFIG_MPC8313 1
38
39#define CONFIG_PCI
Ron Madrid5bb907a2009-01-22 15:05:24 -080040
41#define CONFIG_MISC_INIT_R
42
43/*
44 * On-board devices
45 *
46 * TSEC1 is Marvell PHY 88E1118
47 */
48
49#define CONFIG_SYS_33MHZ
50
51#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
52
53#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
54
55#define CONFIG_SYS_IMMR 0xE0000000
56
57#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
58#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
59#endif
60
61#define CONFIG_SYS_MEMTEST_START 0x00001000
62#define CONFIG_SYS_MEMTEST_END 0x07f00000
63
64#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
65#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
66
67/*
68 * Device configurations
69 */
70#define CONFIG_TSEC1
71
72/*
73 * DDR Setup
74 */
75#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
76#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
77#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
78
79#define CONFIG_VERY_BIG_RAM
80#define CONFIG_MAX_MEM_MAPPED (512 << 20)
81
82#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
83 | DDRCDR_PZ_NOMZ \
84 | DDRCDR_NZ_NOMZ \
85 | DDRCDR_M_ODR )
86 /* 0x73000002 TODO ODR & DRN ? */
87
88/*
89 * FLASH on the Local Bus
90 */
91#define CONFIG_SYS_NO_FLASH
92
93#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
94
95#if !defined(CONFIG_NAND_SPL)
96#define CONFIG_SYS_RAMBOOT
97#endif
98
99#define CONFIG_SYS_INIT_RAM_LOCK 1
100#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
101#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
102
103#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
104#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
105#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106
107/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
108#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
109#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
110
111/*
112 * Local Bus LCRR and LBCR regs
113 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500114#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
115#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
116#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Ron Madrid5bb907a2009-01-22 15:05:24 -0800117#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
118 | (0xFF << LBCR_BMT_SHIFT) \
119 | 0xF ) /* 0x0004ff0f */
120
121#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
122
123/* drivers/mtd/nand/nand.c */
124#ifdef CONFIG_NAND_SPL
125#define CONFIG_SYS_NAND_BASE 0xFFF00000
126#else
127#define CONFIG_SYS_NAND_BASE 0xE2800000
128#endif
129
130#define CONFIG_SYS_MAX_NAND_DEVICE 1
131#define NAND_MAX_CHIPS 1
132#define CONFIG_MTD_NAND_VERIFY_WRITE
133#define CONFIG_CMD_NAND 1
134#define CONFIG_NAND_FSL_ELBC 1
135
136#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
137#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
138#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
139#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
Mingkai Hu6e1385d2009-09-11 10:53:08 +0800140#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800141
142#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
143 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
144 | BR_PS_8 /* Port Size = 8 bit */ \
145 | BR_MS_FCM /* MSEL = FCM */ \
146 | BR_V ) /* valid */
147
148#ifdef CONFIG_NAND_SP
149#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
150 | OR_FCM_CSCT \
151 | OR_FCM_CST \
152 | OR_FCM_CHT \
153 | OR_FCM_SCY_1 \
154 | OR_FCM_TRLX \
155 | OR_FCM_EHTR )
156#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
157#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
158#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
159#define NAND_CACHE_PAGES 32
160#elif defined(CONFIG_NAND_LP)
161#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
162 | OR_FCM_PGS \
163 | OR_FCM_CSCT \
164 | OR_FCM_CST \
165 | OR_FCM_CHT \
166 | OR_FCM_SCY_1 \
167 | OR_FCM_TRLX \
168 | OR_FCM_EHTR )
169#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
170#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
171#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
172#define NAND_CACHE_PAGES 64
173#else
174#error Page size of NAND not defined.
175#endif /* CONFIG_NAND_SP */
176
177#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
178
179#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
180#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
181
182#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
183
184#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
185#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
186
187/*
188 * JFFS2 configuration
189 */
190#define CONFIG_JFFS2_NAND
191#define CONFIG_JFFS2_DEV "nand0"
192
193/* mtdparts command line support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100194#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200195#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800196#define MTDIDS_DEFAULT "nand0=nand0"
197#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
198
199/* pass open firmware flat tree */
200#define CONFIG_OF_LIBFDT 1
201#define CONFIG_OF_BOARD_SETUP 1
202#define CONFIG_OF_STDOUT_VIA_ALIAS 1
203
204/*
205 * Serial Port
206 */
207#define CONFIG_CONS_INDEX 1
208#define CONFIG_SYS_NS16550
209#define CONFIG_SYS_NS16550_SERIAL
210#define CONFIG_SYS_NS16550_REG_SIZE 1
Ron Madridf5675aa2009-02-18 14:30:44 -0800211#ifdef CONFIG_NAND_SPL
212#define CONFIG_NS16550_MIN_FUNCTIONS
213#endif
Ron Madrid5bb907a2009-01-22 15:05:24 -0800214
215#define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217
218#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
219#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
220
221/* Use the HUSH parser */
222#define CONFIG_SYS_HUSH_PARSER
223#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
224
225/* I2C */
226#define CONFIG_HARD_I2C /* I2C with hardware support*/
227#define CONFIG_FSL_I2C
228#define CONFIG_I2C_MULTI_BUS
Ron Madrid5bb907a2009-01-22 15:05:24 -0800229#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
230#define CONFIG_SYS_I2C_SLAVE 0x7F
231#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
232#define CONFIG_SYS_I2C_OFFSET 0x3000
233#define CONFIG_SYS_I2C2_OFFSET 0x3100
234
235/*
236 * General PCI
237 * Addresses are mapped 1-1.
238 */
239#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
240#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
241#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
242#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
243#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
244#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
245#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
246#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
247#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
248
249#define CONFIG_PCI_PNP /* do pci plug-and-play */
250#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
251
252/*
253 * TSEC
254 */
255#define CONFIG_TSEC_ENET /* TSEC ethernet support */
256
257#define CONFIG_NET_MULTI
258#define CONFIG_GMII /* MII PHY management */
259
260#ifdef CONFIG_TSEC1
261#define CONFIG_HAS_ETH0
262#define CONFIG_TSEC1_NAME "TSEC0"
263#define CONFIG_SYS_TSEC1_OFFSET 0x24000
264#define TSEC1_PHY_ADDR 0x0
265#define TSEC1_FLAGS TSEC_GIGABIT
266#define TSEC1_PHYIDX 0
267#endif
268
269#ifdef CONFIG_TSEC2
270#define CONFIG_HAS_ETH1
271#define CONFIG_TSEC2_NAME "TSEC1"
272#define CONFIG_SYS_TSEC2_OFFSET 0x25000
273#define TSEC2_PHY_ADDR 4
274#define TSEC2_FLAGS TSEC_GIGABIT
275#define TSEC2_PHYIDX 0
276#endif
277
278
279/* Options are: TSEC[0-1] */
280#define CONFIG_ETHPRIME "TSEC1"
281
282/*
283 * Configure on-board RTC
284 */
285#define CONFIG_RTC_DS1337
286#define CONFIG_SYS_I2C_RTC_ADDR 0x68
287
288/*
289 * Environment
290 */
291#if defined(CONFIG_NAND_U_BOOT)
292 #define CONFIG_ENV_IS_IN_NAND 1
293 #define CONFIG_ENV_OFFSET (768 * 1024)
294 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
295 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
296 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
297 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
298 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
299#elif !defined(CONFIG_SYS_RAMBOOT)
300 #define CONFIG_ENV_IS_IN_FLASH 1
301 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
302 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
303 #define CONFIG_ENV_SIZE 0x2000
304
305/* Address and size of Redundant Environment Sector */
306#else
307 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
308 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
309 #define CONFIG_ENV_SIZE 0x2000
310#endif
311
312#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
313#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
314
315/*
316 * BOOTP options
317 */
318#define CONFIG_BOOTP_BOOTFILESIZE
319#define CONFIG_BOOTP_BOOTPATH
320#define CONFIG_BOOTP_GATEWAY
321#define CONFIG_BOOTP_HOSTNAME
322
323
324/*
325 * Command line configuration.
326 */
327#include <config_cmd_default.h>
328#undef CONFIG_CMD_IMLS
329#undef CONFIG_CMD_FLASH
330
331#define CONFIG_CMD_PING
332#define CONFIG_CMD_DHCP
333#define CONFIG_CMD_I2C
334#define CONFIG_CMD_MII
335#define CONFIG_CMD_DATE
336#define CONFIG_CMD_PCI
337#define CONFIG_CMD_JFFS2
338
339#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500340 #undef CONFIG_CMD_SAVEENV
Ron Madrid5bb907a2009-01-22 15:05:24 -0800341 #undef CONFIG_CMD_LOADS
342#endif
343
344#define CONFIG_CMDLINE_EDITING 1
345
346
347/*
348 * Miscellaneous configurable options
349 */
350#define CONFIG_SYS_LONGHELP /* undef to save memory */
351#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
352#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
353#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
354
355#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
356 + sizeof(CONFIG_SYS_PROMPT) \
357 + 16 ) /* Print Buffer Size */
358#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
359#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
360#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
361
362/*
363 * For booting Linux, the board info and command line data
364 * have to be in the first 8 MB of memory, since this is
365 * the maximum mapped by the Linux kernel during initialization.
366 */
367#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
368
369#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
370
371#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
372 | 0x20000000 /* reserved */ \
373 | HRCWL_DDR_TO_SCB_CLK_2X1 \
374 | HRCWL_CSB_TO_CLKIN_4X1 \
375 | HRCWL_CORE_TO_CSB_2_5X1 )
376
377#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
378
379#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
380 | HRCWH_PCI1_ARBITER_ENABLE \
381 | HRCWH_CORE_ENABLE \
382 | HRCWH_BOOTSEQ_DISABLE \
383 | HRCWH_SW_WATCHDOG_DISABLE \
384 | HRCWH_TSEC1M_IN_RGMII \
385 | HRCWH_TSEC2M_IN_RGMII \
386 | HRCWH_BIG_ENDIAN \
387 | HRCWH_LALE_NORMAL )
388
389#ifdef CONFIG_NAND_LP
390#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
391 | HRCWH_FROM_0XFFF00100 \
392 | HRCWH_ROM_LOC_NAND_LP_8BIT \
393 | HRCWH_RL_EXT_NAND)
394#else
395#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
396 | HRCWH_FROM_0XFFF00100 \
397 | HRCWH_ROM_LOC_NAND_SP_8BIT \
398 | HRCWH_RL_EXT_NAND )
399#endif
400
401/* System IO Config */
402#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
403 | SICRH_ETSEC2_C \
404 | SICRH_ETSEC2_D \
405 | SICRH_ETSEC2_E \
406 | SICRH_ETSEC2_F \
407 | SICRH_ETSEC2_G \
408 | SICRH_TSOBI1 \
409 | SICRH_TSOBI2 )
410#define CONFIG_SYS_SICRL (SICRL_USBDR \
411 | SICRL_ETSEC2_A )
412
413#define CONFIG_SYS_HID0_INIT 0x000000000
414#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
415 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
416
417#define CONFIG_SYS_HID2 HID2_HBE
418
419#define CONFIG_HIGH_BATS 1 /* High BATs supported */
420
421/* DDR @ 0x00000000 */
422#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
423#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
424#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
425#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
426
427/* PCI @ 0x80000000 */
428#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
429#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
430#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
431#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
432
433/* PCI2 not supported on 8313 */
434#define CONFIG_SYS_IBAT4L (0)
435#define CONFIG_SYS_IBAT4U (0)
436
437/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
438#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
439#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
440
441/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Scott Woodc1230982009-03-31 17:49:36 -0500442#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800443#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
444
445#define CONFIG_SYS_IBAT7L (0)
446#define CONFIG_SYS_IBAT7U (0)
447
448#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
449#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
450#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
451#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
452#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
453#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
454#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
455#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
456#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
457#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
458#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
459#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
460#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
461#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
462#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
463#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
464
465/*
466 * Internal Definitions
467 *
468 * Boot Flags
469 */
470#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
471#define BOOTFLAG_WARM 0x02 /* Software reboot */
472
473/*
474 * Environment Configuration
475 */
476#define CONFIG_ENV_OVERWRITE
477
478#define CONFIG_NETDEV eth1
479
480#define CONFIG_HOSTNAME simpc8313
481#define CONFIG_ROOTPATH /tftpboot/
482#define CONFIG_BOOTFILE /tftpboot/uImage
483#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
484#define CONFIG_FDTFILE simpc8313.dtb
485
486#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
487#define CONFIG_BOOTDELAY 5 /* 5 second delay */
488#define CONFIG_BAUDRATE 115200
489
490#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
491
492#define XMK_STR(x) #x
493#define MK_STR(x) XMK_STR(x)
494
495#define CONFIG_EXTRA_ENV_SETTINGS \
496 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
497 "ethprime=TSEC1\0" \
498 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
499 "tftpflash=tftpboot $loadaddr $uboot; " \
500 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
501 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
502 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
503 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
504 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
505 "fdtaddr=ae0000\0" \
506 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
507 "console=ttyS0\0" \
508 "setbootargs=setenv bootargs " \
509 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
510 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
511 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
512 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
513 "load_uboot=tftp 100000 u-boot-nand.bin\0" \
514 "burn_uboot=nand erase u-boot 80000; " \
515 "nand write 100000 u-boot $filesize\0" \
516 "update_uboot=run load_uboot;run burn_uboot\0" \
517 "mtdids=nand0=nand0\0" \
518 "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
519 "nfsargs=setenv bootargs root=/dev/nfs rw " \
520 "nfsroot=${serverip}:${rootpath}\0" \
521 "ramargs=setenv bootargs root=/dev/ram rw\0" \
522 "addip=setenv bootargs ${bootargs} " \
523 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
524 ":${hostname}:${netdev}:off panic=1\0" \
525 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
526 "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
527 "console=ttyS0,115200\0" \
528 ""
529
530#define CONFIG_NFSBOOTCOMMAND \
531 "setenv rootdev /dev/nfs;" \
532 "run setbootargs;" \
533 "run setipargs;" \
534 "tftp $loadaddr $bootfile;" \
535 "tftp $fdtaddr $fdtfile;" \
536 "bootm $loadaddr - $fdtaddr"
537
538#define CONFIG_RAMBOOTCOMMAND \
539 "setenv rootdev /dev/ram;" \
540 "run setbootargs;" \
541 "tftp $ramdiskaddr $ramdiskfile;" \
542 "tftp $loadaddr $bootfile;" \
543 "tftp $fdtaddr $fdtfile;" \
544 "bootm $loadaddr $ramdiskaddr $fdtaddr"
545
546#undef MK_STR
547#undef XMK_STR
548
549#endif /* __CONFIG_H */