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Mark Jackson13b50fe2008-07-30 13:07:27 +01001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#include <asm/arch/memory-map.h>
28
29#define CONFIG_AVR32 1
30#define CONFIG_AT32AP 1
31#define CONFIG_AT32AP7000 1
32#define CONFIG_MIMC200 1
33
34#define CONFIG_MIMC200_EXT_FLASH 1
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_HZ 1000
Mark Jackson13b50fe2008-07-30 13:07:27 +010037
38/*
39 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
40 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
41 * and the PBA bus to run at 1/4 the PLL frequency.
42 */
43#define CONFIG_PLL 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_POWER_MANAGER 1
45#define CONFIG_SYS_OSC0_HZ 10000000
46#define CONFIG_SYS_PLL0_DIV 1
47#define CONFIG_SYS_PLL0_MUL 15
48#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
49#define CONFIG_SYS_CLKDIV_CPU 0
50#define CONFIG_SYS_CLKDIV_HSB 1
51#define CONFIG_SYS_CLKDIV_PBA 2
52#define CONFIG_SYS_CLKDIV_PBB 1
Mark Jackson13b50fe2008-07-30 13:07:27 +010053
54/*
55 * The PLLOPT register controls the PLL like this:
56 * icp = PLLOPT<2>
57 * ivco = PLLOPT<1:0>
58 *
59 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
60 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_PLL0_OPT 0x04
Mark Jackson13b50fe2008-07-30 13:07:27 +010062
63#define CONFIG_USART1 1
64#define CONFIG_MIMC200_DBGLINK 1
65
66/* User serviceable stuff */
67#define CONFIG_DOS_PARTITION 1
68
69#define CONFIG_CMDLINE_TAG 1
70#define CONFIG_SETUP_MEMORY_TAGS 1
71#define CONFIG_INITRD_TAG 1
72
73#define CONFIG_STACKSIZE (2048)
74
75#define CONFIG_BAUDRATE 115200
76#define CONFIG_BOOTARGS \
Mark Jacksonc0356a82009-08-17 16:42:52 +010077 "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
Mark Jackson13b50fe2008-07-30 13:07:27 +010078#define CONFIG_BOOTCOMMAND \
Mark Jacksona69a4232008-10-03 11:48:57 +010079 "fsload boot/uImage; bootm"
Mark Jackson13b50fe2008-07-30 13:07:27 +010080
81#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
Mark Jacksona69a4232008-10-03 11:48:57 +010082#define CONFIG_DISABLE_CONSOLE 1 /* disable console */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Mark Jackson13b50fe2008-07-30 13:07:27 +010084
Mark Jacksonf68378d2009-07-21 11:35:22 +010085#define CONFIG_LCD 1
86
Mark Jackson13b50fe2008-07-30 13:07:27 +010087/*
88 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
89 * data on the serial line may interrupt the boot sequence.
90 */
91#define CONFIG_BOOTDELAY 0
92#define CONFIG_ZERO_BOOTDELAY_CHECK 1
93#define CONFIG_AUTOBOOT 1
94
95/*
96 * After booting the board for the first time, new ethernet addresses
97 * should be generated and assigned to the environment variables
98 * "ethaddr" and "eth1addr". This is normally done during production.
99 */
100#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
101#define CONFIG_NET_MULTI 1
102
103/*
104 * BOOTP/DHCP options
105 */
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108
109#define CONFIG_DOS_PARTITION 1
110
111/*
112 * Command line configuration.
113 */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_ASKENV
117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_EXT2
119#define CONFIG_CMD_FAT
120#define CONFIG_CMD_JFFS2
121#define CONFIG_CMD_MMC
122#define CONFIG_CMD_NET
123
124#define CONFIG_ATMEL_USART 1
125#define CONFIG_MACB 1
Haavard Skinnemoenab0df362008-08-29 21:09:49 +0200126#define CONFIG_PORTMUX_PIO 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_NR_PIOS 5
128#define CONFIG_SYS_HSDRAMC 1
Mark Jackson13b50fe2008-07-30 13:07:27 +0100129#define CONFIG_MMC 1
130#define CONFIG_ATMEL_MCI 1
131
Mark Jacksonf68378d2009-07-21 11:35:22 +0100132#if defined(CONFIG_LCD)
133#define CONFIG_CMD_BMP
134#define CONFIG_ATMEL_LCD 1
135#define LCD_BPP LCD_COLOR16
136#define CONFIG_BMP_16BPP 1
137#define CONFIG_FB_ADDR 0x10600000
138#define CONFIG_WHITE_ON_BLACK 1
139#define CONFIG_VIDEO_BMP_GZIP 1
140#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
141#define CONFIG_ATMEL_LCD_BGR555 1
142#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
143#define CONFIG_SPLASH_SCREEN 1
144#endif
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_DCACHE_LINESZ 32
147#define CONFIG_SYS_ICACHE_LINESZ 32
Mark Jackson13b50fe2008-07-30 13:07:27 +0100148
149#define CONFIG_NR_DRAM_BANKS 1
150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_FLASH_CFI 1
Haavard Skinnemoen49267142008-08-20 09:40:16 +0200152#define CONFIG_FLASH_CFI_DRIVER 1
Mark Jackson13b50fe2008-07-30 13:07:27 +0100153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_BASE 0x00000000
155#define CONFIG_SYS_FLASH_SIZE 0x800000
156#define CONFIG_SYS_MAX_FLASH_BANKS 1
157#define CONFIG_SYS_MAX_FLASH_SECT 135
Mark Jackson13b50fe2008-07-30 13:07:27 +0100158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Mark Jackson13b50fe2008-07-30 13:07:27 +0100160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
162#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
163#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Mark Jackson13b50fe2008-07-30 13:07:27 +0100164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_FRAM_BASE 0x08000000
166#define CONFIG_SYS_FRAM_SIZE 0x20000
Mark Jackson13b50fe2008-07-30 13:07:27 +0100167
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200168#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200169#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MALLOC_LEN (1024*1024)
175#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100176
177/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
179#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100180
181/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_PROMPT "U-Boot> "
183#define CONFIG_SYS_CBSIZE 256
184#define CONFIG_SYS_MAXARGS 16
185#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
186#define CONFIG_SYS_LONGHELP 1
Mark Jackson13b50fe2008-07-30 13:07:27 +0100187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
189#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Mark Jackson13b50fe2008-07-30 13:07:27 +0100192
193#endif /* __CONFIG_H */