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Stefan Roese1eac2a72006-11-29 15:42:37 +01001/*
2 * (C) Copyright 2003
3 * Ingo Assmus <ingo.assmus@keymile.com>
4 *
5 * based on - Driver for MV64460X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * mv_eth.h - header file for the polled mode GT ethernet driver
29 */
30
31#ifndef __DB64460_ETH_H__
32#define __DB64460_ETH_H__
33
34#include <asm/types.h>
35#include <asm/io.h>
36#include <asm/byteorder.h>
37#include <common.h>
38#include <net.h>
39#include "mv_regs.h"
40#include "ppc_error_no.h"
41#include "../../Marvell/include/core.h"
42
43/*************************************************************************
44**************************************************************************
45**************************************************************************
46* The first part is the high level driver of the gigE ethernet ports. *
47**************************************************************************
48**************************************************************************
49*************************************************************************/
50#ifndef TRUE
51#define TRUE 1
52#endif
53#ifndef FALSE
54#define FALSE 0
55#endif
56
57/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
58#ifndef MAX_SKB_FRAGS
59#define MAX_SKB_FRAGS 0
60#endif
61
62/* Port attributes */
63/*#define MAX_RX_QUEUE_NUM 8*/
64/*#define MAX_TX_QUEUE_NUM 8*/
65#define MAX_RX_QUEUE_NUM 1
66#define MAX_TX_QUEUE_NUM 1
67
68
69/* Use one TX queue and one RX queue */
70#define MV64460_TX_QUEUE_NUM 1
71#define MV64460_RX_QUEUE_NUM 1
72
73/*
74 * Number of RX / TX descriptors on RX / TX rings.
75 * Note that allocating RX descriptors is done by allocating the RX
76 * ring AND a preallocated RX buffers (skb's) for each descriptor.
77 * The TX descriptors only allocates the TX descriptors ring,
78 * with no pre allocated TX buffers (skb's are allocated by higher layers.
79 */
80
81/* Default TX ring size is 10 descriptors */
82#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
83#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
84#else
85#define MV64460_TX_QUEUE_SIZE 4
86#endif
87
88/* Default RX ring size is 4 descriptors */
89#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
90#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
91#else
92#define MV64460_RX_QUEUE_SIZE 4
93#endif
94
95#ifdef CONFIG_RX_BUFFER_SIZE
96#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
97#else
98#define MV64460_RX_BUFFER_SIZE 1600
99#endif
100
101#ifdef CONFIG_TX_BUFFER_SIZE
102#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
103#else
104#define MV64460_TX_BUFFER_SIZE 1600
105#endif
106
107/*
108 * Network device statistics. Akin to the 2.0 ether stats but
109 * with byte counters.
110 */
111
112struct net_device_stats
113{
114 unsigned long rx_packets; /* total packets received */
115 unsigned long tx_packets; /* total packets transmitted */
116 unsigned long rx_bytes; /* total bytes received */
117 unsigned long tx_bytes; /* total bytes transmitted */
118 unsigned long rx_errors; /* bad packets received */
119 unsigned long tx_errors; /* packet transmit problems */
120 unsigned long rx_dropped; /* no space in linux buffers */
121 unsigned long tx_dropped; /* no space available in linux */
122 unsigned long multicast; /* multicast packets received */
123 unsigned long collisions;
124
125 /* detailed rx_errors: */
126 unsigned long rx_length_errors;
127 unsigned long rx_over_errors; /* receiver ring buff overflow */
128 unsigned long rx_crc_errors; /* recved pkt with crc error */
129 unsigned long rx_frame_errors; /* recv'd frame alignment error */
130 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
131 unsigned long rx_missed_errors; /* receiver missed packet */
132
133 /* detailed tx_errors */
134 unsigned long tx_aborted_errors;
135 unsigned long tx_carrier_errors;
136 unsigned long tx_fifo_errors;
137 unsigned long tx_heartbeat_errors;
138 unsigned long tx_window_errors;
139
140 /* for cslip etc */
141 unsigned long rx_compressed;
142 unsigned long tx_compressed;
143};
144
145
146/* Private data structure used for ethernet device */
147struct mv64460_eth_priv {
148 unsigned int port_num;
149 struct net_device_stats *stats;
150
151 /* to buffer area aligned */
152 char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
153 char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
154
155 /* Size of Tx Ring per queue */
156 unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
157
158 /* Size of Rx Ring per queue */
159 unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
160
161 /* Magic Number for Ethernet running */
162 unsigned int eth_running;
163
164 int first_init;
165};
166
167int mv64460_eth_init (struct eth_device *dev);
168int mv64460_eth_stop (struct eth_device *dev);
169int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
170/* return db64460_eth0_poll(); */
171
172int mv64460_eth_open (struct eth_device *dev);
173
174
175/*************************************************************************
176**************************************************************************
177**************************************************************************
178* The second part is the low level driver of the gigE ethernet ports. *
179**************************************************************************
180**************************************************************************
181*************************************************************************/
182
183
184/********************************************************************************
185 * Header File for : MV-643xx network interface header
186 *
187 * DESCRIPTION:
188 * This header file contains macros typedefs and function declaration for
189 * the Marvell Gig Bit Ethernet Controller.
190 *
191 * DEPENDENCIES:
192 * None.
193 *
194 *******************************************************************************/
195
196
197#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
198#ifdef CONFIG_MV64460_SRAM_CACHEABLE
199/* In case SRAM is cacheable but not cache coherent */
200#define D_CACHE_FLUSH_LINE(addr, offset) \
201{ \
202 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
203}
204#else
205/* In case SRAM is cache coherent or non-cacheable */
206#define D_CACHE_FLUSH_LINE(addr, offset) ;
207#endif
208#else
209#ifdef CONFIG_NOT_COHERENT_CACHE
210/* In case of descriptors on DDR but not cache coherent */
211#define D_CACHE_FLUSH_LINE(addr, offset) \
212{ \
213 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
214}
215#else
216/* In case of descriptors on DDR and cache coherent */
217#define D_CACHE_FLUSH_LINE(addr, offset) ;
218#endif /* CONFIG_NOT_COHERENT_CACHE */
219#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
220
221
222#define CPU_PIPE_FLUSH \
223{ \
224 __asm__ __volatile__ ("eieio"); \
225}
226
227
228/* defines */
229
230/* Default port configuration value */
231#define PORT_CONFIG_VALUE \
232 ETH_UNICAST_NORMAL_MODE | \
233 ETH_DEFAULT_RX_QUEUE_0 | \
234 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
235 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
236 ETH_RECEIVE_BC_IF_IP | \
237 ETH_RECEIVE_BC_IF_ARP | \
238 ETH_CAPTURE_TCP_FRAMES_DIS | \
239 ETH_CAPTURE_UDP_FRAMES_DIS | \
240 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
241 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
242 ETH_DEFAULT_RX_BPDU_QUEUE_0
243
244/* Default port extend configuration value */
245#define PORT_CONFIG_EXTEND_VALUE \
246 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
247 ETH_PARTITION_DISABLE
248
249
250/* Default sdma control value */
251#ifdef CONFIG_NOT_COHERENT_CACHE
252#define PORT_SDMA_CONFIG_VALUE \
253 ETH_RX_BURST_SIZE_16_64BIT | \
254 GT_ETH_IPG_INT_RX(0) | \
255 ETH_TX_BURST_SIZE_16_64BIT;
256#else
257#define PORT_SDMA_CONFIG_VALUE \
258 ETH_RX_BURST_SIZE_4_64BIT | \
259 GT_ETH_IPG_INT_RX(0) | \
260 ETH_TX_BURST_SIZE_4_64BIT;
261#endif
262
263#define GT_ETH_IPG_INT_RX(value) \
264 ((value & 0x3fff) << 8)
265
266/* Default port serial control value */
267#define PORT_SERIAL_CONTROL_VALUE \
268 ETH_FORCE_LINK_PASS | \
269 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
270 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
271 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
272 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
273 ETH_FORCE_BP_MODE_NO_JAM | \
274 BIT9 | \
275 ETH_DO_NOT_FORCE_LINK_FAIL | \
276 ETH_RETRANSMIT_16_ETTEMPTS | \
277 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
278 ETH_DTE_ADV_0 | \
279 ETH_DISABLE_AUTO_NEG_BYPASS | \
280 ETH_AUTO_NEG_NO_CHANGE | \
281 ETH_MAX_RX_PACKET_1552BYTE | \
282 ETH_CLR_EXT_LOOPBACK | \
283 ETH_SET_FULL_DUPLEX_MODE | \
284 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
285
286#define RX_BUFFER_MAX_SIZE 0xFFFF
287#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
288
289#define RX_BUFFER_MIN_SIZE 0x8
290#define TX_BUFFER_MIN_SIZE 0x8
291
292/* Tx WRR confoguration macros */
293#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
294#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
295#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
296
297/* MAC accepet/reject macros */
298#define ACCEPT_MAC_ADDR 0
299#define REJECT_MAC_ADDR 1
300
301/* Size of a Tx/Rx descriptor used in chain list data structure */
302#define RX_DESC_ALIGNED_SIZE 0x20
303#define TX_DESC_ALIGNED_SIZE 0x20
304
305/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
306#define TX_BUF_OFFSET_IN_DESC 0x18
307/* Buffer offset from buffer pointer */
308#define RX_BUF_OFFSET 0x2
309
310/* Gap define */
311#define ETH_BAR_GAP 0x8
312#define ETH_SIZE_REG_GAP 0x8
313#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
314#define ETH_PORT_ACCESS_CTRL_GAP 0x4
315
316/* Gigabit Ethernet Unit Global Registers */
317
318/* MIB Counters register definitions */
319#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
320#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
321#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
322#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
323#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
324#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
325#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
326#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
327#define ETH_MIB_FRAMES_64_OCTETS 0x20
328#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
329#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
330#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
331#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
332#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
333#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
334#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
335#define ETH_MIB_GOOD_FRAMES_SENT 0x40
336#define ETH_MIB_EXCESSIVE_COLLISION 0x44
337#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
338#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
339#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
340#define ETH_MIB_FC_SENT 0x54
341#define ETH_MIB_GOOD_FC_RECEIVED 0x58
342#define ETH_MIB_BAD_FC_RECEIVED 0x5c
343#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
344#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
345#define ETH_MIB_OVERSIZE_RECEIVED 0x68
346#define ETH_MIB_JABBER_RECEIVED 0x6c
347#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
348#define ETH_MIB_BAD_CRC_EVENT 0x74
349#define ETH_MIB_COLLISION 0x78
350#define ETH_MIB_LATE_COLLISION 0x7c
351
352/* Port serial status reg (PSR) */
353#define ETH_INTERFACE_GMII_MII 0
354#define ETH_INTERFACE_PCM BIT0
355#define ETH_LINK_IS_DOWN 0
356#define ETH_LINK_IS_UP BIT1
357#define ETH_PORT_AT_HALF_DUPLEX 0
358#define ETH_PORT_AT_FULL_DUPLEX BIT2
359#define ETH_RX_FLOW_CTRL_DISABLED 0
360#define ETH_RX_FLOW_CTRL_ENBALED BIT3
361#define ETH_GMII_SPEED_100_10 0
362#define ETH_GMII_SPEED_1000 BIT4
363#define ETH_MII_SPEED_10 0
364#define ETH_MII_SPEED_100 BIT5
365#define ETH_NO_TX 0
366#define ETH_TX_IN_PROGRESS BIT7
367#define ETH_BYPASS_NO_ACTIVE 0
368#define ETH_BYPASS_ACTIVE BIT8
369#define ETH_PORT_NOT_AT_PARTITION_STATE 0
370#define ETH_PORT_AT_PARTITION_STATE BIT9
371#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
372#define ETH_PORT_TX_FIFO_EMPTY BIT10
373
374
375/* These macros describes the Port configuration reg (Px_cR) bits */
376#define ETH_UNICAST_NORMAL_MODE 0
377#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
378#define ETH_DEFAULT_RX_QUEUE_0 0
379#define ETH_DEFAULT_RX_QUEUE_1 BIT1
380#define ETH_DEFAULT_RX_QUEUE_2 BIT2
381#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
382#define ETH_DEFAULT_RX_QUEUE_4 BIT3
383#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
384#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
385#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
386#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
387#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
388#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
389#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
390#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
391#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
392#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
393#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
394#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
395#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
396#define ETH_RECEIVE_BC_IF_IP 0
397#define ETH_REJECT_BC_IF_IP BIT8
398#define ETH_RECEIVE_BC_IF_ARP 0
399#define ETH_REJECT_BC_IF_ARP BIT9
400#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
401#define ETH_CAPTURE_TCP_FRAMES_DIS 0
402#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
403#define ETH_CAPTURE_UDP_FRAMES_DIS 0
404#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
405#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
406#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
407#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
408#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
409#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
410#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
411#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
412#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
413#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
414#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
415#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
416#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
417#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
418#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
419#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
420#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
421#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
422#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
423#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
424#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
425#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
426#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
427#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
428#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
429
430
431/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
432#define ETH_CLASSIFY_EN BIT0
433#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
434#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
435#define ETH_PARTITION_DISABLE 0
436#define ETH_PARTITION_ENABLE BIT2
437
438
439/* Tx/Rx queue command reg (RQCR/TQCR)*/
440#define ETH_QUEUE_0_ENABLE BIT0
441#define ETH_QUEUE_1_ENABLE BIT1
442#define ETH_QUEUE_2_ENABLE BIT2
443#define ETH_QUEUE_3_ENABLE BIT3
444#define ETH_QUEUE_4_ENABLE BIT4
445#define ETH_QUEUE_5_ENABLE BIT5
446#define ETH_QUEUE_6_ENABLE BIT6
447#define ETH_QUEUE_7_ENABLE BIT7
448#define ETH_QUEUE_0_DISABLE BIT8
449#define ETH_QUEUE_1_DISABLE BIT9
450#define ETH_QUEUE_2_DISABLE BIT10
451#define ETH_QUEUE_3_DISABLE BIT11
452#define ETH_QUEUE_4_DISABLE BIT12
453#define ETH_QUEUE_5_DISABLE BIT13
454#define ETH_QUEUE_6_DISABLE BIT14
455#define ETH_QUEUE_7_DISABLE BIT15
456
457/* These macros describes the Port Sdma configuration reg (SDCR) bits */
458#define ETH_RIFB BIT0
459#define ETH_RX_BURST_SIZE_1_64BIT 0
460#define ETH_RX_BURST_SIZE_2_64BIT BIT1
461#define ETH_RX_BURST_SIZE_4_64BIT BIT2
462#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
463#define ETH_RX_BURST_SIZE_16_64BIT BIT3
464#define ETH_BLM_RX_NO_SWAP BIT4
465#define ETH_BLM_RX_BYTE_SWAP 0
466#define ETH_BLM_TX_NO_SWAP BIT5
467#define ETH_BLM_TX_BYTE_SWAP 0
468#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
469#define ETH_DESCRIPTORS_NO_SWAP 0
470#define ETH_TX_BURST_SIZE_1_64BIT 0
471#define ETH_TX_BURST_SIZE_2_64BIT BIT22
472#define ETH_TX_BURST_SIZE_4_64BIT BIT23
473#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
474#define ETH_TX_BURST_SIZE_16_64BIT BIT24
475
476/* These macros describes the Port serial control reg (PSCR) bits */
477#define ETH_SERIAL_PORT_DISABLE 0
478#define ETH_SERIAL_PORT_ENABLE BIT0
479#define ETH_FORCE_LINK_PASS BIT1
480#define ETH_DO_NOT_FORCE_LINK_PASS 0
481#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
482#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
483#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
484#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
485#define ETH_ADV_NO_FLOW_CTRL 0
486#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
487#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
488#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
489#define ETH_FORCE_BP_MODE_NO_JAM 0
490#define ETH_FORCE_BP_MODE_JAM_TX BIT7
491#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
492#define ETH_FORCE_LINK_FAIL 0
493#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
494#define ETH_RETRANSMIT_16_ETTEMPTS 0
495#define ETH_RETRANSMIT_FOREVER BIT11
496#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
497#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
498#define ETH_DTE_ADV_0 0
499#define ETH_DTE_ADV_1 BIT14
500#define ETH_DISABLE_AUTO_NEG_BYPASS 0
501#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
502#define ETH_AUTO_NEG_NO_CHANGE 0
503#define ETH_RESTART_AUTO_NEG BIT16
504#define ETH_MAX_RX_PACKET_1518BYTE 0
505#define ETH_MAX_RX_PACKET_1522BYTE BIT17
506#define ETH_MAX_RX_PACKET_1552BYTE BIT18
507#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
508#define ETH_MAX_RX_PACKET_9192BYTE BIT19
509#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
510#define ETH_SET_EXT_LOOPBACK BIT20
511#define ETH_CLR_EXT_LOOPBACK 0
512#define ETH_SET_FULL_DUPLEX_MODE BIT21
513#define ETH_SET_HALF_DUPLEX_MODE 0
514#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
515#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
516#define ETH_SET_GMII_SPEED_TO_10_100 0
517#define ETH_SET_GMII_SPEED_TO_1000 BIT23
518#define ETH_SET_MII_SPEED_TO_10 0
519#define ETH_SET_MII_SPEED_TO_100 BIT24
520
521
522/* SMI reg */
523#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
524#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
525#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
526#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
527
528/* SDMA command status fields macros */
529
530/* Tx & Rx descriptors status */
531#define ETH_ERROR_SUMMARY (BIT0)
532
533/* Tx & Rx descriptors command */
534#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
535
536/* Tx descriptors status */
537#define ETH_LC_ERROR (0 )
538#define ETH_UR_ERROR (BIT1 )
539#define ETH_RL_ERROR (BIT2 )
540#define ETH_LLC_SNAP_FORMAT (BIT9 )
541
542/* Rx descriptors status */
543#define ETH_CRC_ERROR (0 )
544#define ETH_OVERRUN_ERROR (BIT1 )
545#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
546#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
547#define ETH_VLAN_TAGGED (BIT19)
548#define ETH_BPDU_FRAME (BIT20)
549#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
550#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
551#define ETH_OTHER_FRAME_TYPE (BIT22)
552#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
553#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
554#define ETH_FRAME_HEADER_OK (BIT25)
555#define ETH_RX_LAST_DESC (BIT26)
556#define ETH_RX_FIRST_DESC (BIT27)
557#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
558#define ETH_RX_ENABLE_INTERRUPT (BIT29)
559#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
560
561/* Rx descriptors byte count */
562#define ETH_FRAME_FRAGMENTED (BIT2)
563
564/* Tx descriptors command */
565#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
566#define ETH_FRAME_SET_TO_VLAN (BIT15)
567#define ETH_TCP_FRAME (0 )
568#define ETH_UDP_FRAME (BIT16)
569#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
570#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
571#define ETH_ZERO_PADDING (BIT19)
572#define ETH_TX_LAST_DESC (BIT20)
573#define ETH_TX_FIRST_DESC (BIT21)
574#define ETH_GEN_CRC (BIT22)
575#define ETH_TX_ENABLE_INTERRUPT (BIT23)
576#define ETH_AUTO_MODE (BIT30)
577
578/* Address decode parameters */
579/* Ethernet Base Address Register bits */
580#define EBAR_TARGET_DRAM 0x00000000
581#define EBAR_TARGET_DEVICE 0x00000001
582#define EBAR_TARGET_CBS 0x00000002
583#define EBAR_TARGET_PCI0 0x00000003
584#define EBAR_TARGET_PCI1 0x00000004
585#define EBAR_TARGET_CUNIT 0x00000005
586#define EBAR_TARGET_AUNIT 0x00000006
587#define EBAR_TARGET_GUNIT 0x00000007
588
589/* Window attributes */
590#define EBAR_ATTR_DRAM_CS0 0x00000E00
591#define EBAR_ATTR_DRAM_CS1 0x00000D00
592#define EBAR_ATTR_DRAM_CS2 0x00000B00
593#define EBAR_ATTR_DRAM_CS3 0x00000700
594
595/* DRAM Target interface */
596#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
597#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
598#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
599
600/* Device Bus Target interface */
601#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
602#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
603#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
604#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
605#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
606
607/* PCI Target interface */
608#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
609#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
610#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
611#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
612#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
613#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
614#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
615#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
616#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
617#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
618
619/* CPU 60x bus or internal SRAM interface */
620#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
621#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
622#define EBAR_ATTR_CBS_SRAM 0x00000000
623#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
624
625/* Window access control */
626#define EWIN_ACCESS_NOT_ALLOWED 0
627#define EWIN_ACCESS_READ_ONLY BIT0
628#define EWIN_ACCESS_FULL (BIT1 | BIT0)
629#define EWIN0_ACCESS_MASK 0x0003
630#define EWIN1_ACCESS_MASK 0x000C
631#define EWIN2_ACCESS_MASK 0x0030
632#define EWIN3_ACCESS_MASK 0x00C0
633
634/* typedefs */
635
636typedef enum _eth_port
637{
638 ETH_0 = 0,
639 ETH_1 = 1,
640 ETH_2 = 2
641}ETH_PORT;
642
643typedef enum _eth_func_ret_status
644{
645 ETH_OK, /* Returned as expected. */
646 ETH_ERROR, /* Fundamental error. */
647 ETH_RETRY, /* Could not process request. Try later. */
648 ETH_END_OF_JOB, /* Ring has nothing to process. */
649 ETH_QUEUE_FULL, /* Ring resource error. */
650 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
651}ETH_FUNC_RET_STATUS;
652
653typedef enum _eth_queue
654{
655 ETH_Q0 = 0,
656 ETH_Q1 = 1,
657 ETH_Q2 = 2,
658 ETH_Q3 = 3,
659 ETH_Q4 = 4,
660 ETH_Q5 = 5,
661 ETH_Q6 = 6,
662 ETH_Q7 = 7
663} ETH_QUEUE;
664
665typedef enum _addr_win
666{
667 ETH_WIN0,
668 ETH_WIN1,
669 ETH_WIN2,
670 ETH_WIN3,
671 ETH_WIN4,
672 ETH_WIN5
673} ETH_ADDR_WIN;
674
675typedef enum _eth_target
676{
677 ETH_TARGET_DRAM ,
678 ETH_TARGET_DEVICE,
679 ETH_TARGET_CBS ,
680 ETH_TARGET_PCI0 ,
681 ETH_TARGET_PCI1
682}ETH_TARGET;
683
684typedef struct _eth_rx_desc
685{
686 unsigned short byte_cnt ; /* Descriptor buffer byte count */
687 unsigned short buf_size ; /* Buffer size */
688 unsigned int cmd_sts ; /* Descriptor command status */
689 unsigned int next_desc_ptr; /* Next descriptor pointer */
690 unsigned int buf_ptr ; /* Descriptor buffer pointer */
691 unsigned int return_info ; /* User resource return information */
692} ETH_RX_DESC;
693
694
695typedef struct _eth_tx_desc
696{
697 unsigned short byte_cnt ; /* Descriptor buffer byte count */
698 unsigned short l4i_chk ; /* CPU provided TCP Checksum */
699 unsigned int cmd_sts ; /* Descriptor command status */
700 unsigned int next_desc_ptr; /* Next descriptor pointer */
701 unsigned int buf_ptr ; /* Descriptor buffer pointer */
702 unsigned int return_info ; /* User resource return information */
703} ETH_TX_DESC;
704
705/* Unified struct for Rx and Tx operations. The user is not required to */
706/* be familier with neither Tx nor Rx descriptors. */
707typedef struct _pkt_info
708{
709 unsigned short byte_cnt ; /* Descriptor buffer byte count */
710 unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
711 unsigned int cmd_sts ; /* Descriptor command status */
712 unsigned int buf_ptr ; /* Descriptor buffer pointer */
713 unsigned int return_info ; /* User resource return information */
714} PKT_INFO;
715
716
717typedef struct _eth_win_param
718{
719 ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
720 ETH_TARGET target; /* System targets. See ETH_TARGET enum */
721 unsigned short attributes; /* BAR attributes. See above macros. */
722 unsigned int base_addr; /* Window base address in unsigned int form */
723 unsigned int high_addr; /* Window high address in unsigned int form */
724 unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
725 bool enable; /* Enable/disable access to the window. */
726 unsigned short access_ctrl; /* Access ctrl register. see above macros */
727} ETH_WIN_PARAM;
728
729
730/* Ethernet port specific infomation */
731
732typedef struct _eth_port_ctrl
733{
734 ETH_PORT port_num; /* User Ethernet port number */
735 int port_phy_addr; /* User phy address of Ethrnet port */
736 unsigned char port_mac_addr[6]; /* User defined port MAC address. */
737 unsigned int port_config; /* User port configuration value */
738 unsigned int port_config_extend; /* User port config extend value */
739 unsigned int port_sdma_config; /* User port SDMA config value */
740 unsigned int port_serial_control; /* User port serial control value */
741 unsigned int port_tx_queue_command; /* Port active Tx queues summary */
742 unsigned int port_rx_queue_command; /* Port active Rx queues summary */
743
744 /* User function to cast virtual address to CPU bus address */
745 unsigned int (*port_virt_to_phys)(unsigned int addr);
746 /* User scratch pad for user specific data structures */
747 void *port_private;
748
749 bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
750 bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
751
752 /* Tx/Rx rings managment indexes fields. For driver use */
753
754 /* Next available Rx resource */
755 volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
756 /* Returning Rx resource */
757 volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
758
759 /* Next available Tx resource */
760 volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
761 /* Returning Tx resource */
762 volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
763 /* An extra Tx index to support transmit of multiple buffers per packet */
764 volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
765
766 /* Tx/Rx rings size and base variables fields. For driver use */
767
768 volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
769 unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
770 char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
771
772 volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
773 unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
774 char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
775
776} ETH_PORT_INFO;
777
778
779/* ethernet.h API list */
780
781/* Port operation control routines */
782static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
783static void eth_port_reset(ETH_PORT eth_port_num);
784static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
785
786
787/* Port MAC address routines */
788static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
789 unsigned char *p_addr,
790 ETH_QUEUE queue);
791#if 0 /* FIXME */
792static void eth_port_mc_addr (ETH_PORT eth_port_num,
793 unsigned char *p_addr,
794 ETH_QUEUE queue,
795 int option);
796#endif
797
798/* PHY and MIB routines */
799static bool ethernet_phy_reset(ETH_PORT eth_port_num);
800
801static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
802 unsigned int phy_reg,
803 unsigned int value);
804
805static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
806 unsigned int phy_reg,
807 unsigned int* value);
808
809static void eth_clear_mib_counters(ETH_PORT eth_port_num);
810
811/* Port data flow control routines */
812static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
813 ETH_QUEUE tx_queue,
814 PKT_INFO *p_pkt_info);
815static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
816 ETH_QUEUE tx_queue,
817 PKT_INFO *p_pkt_info);
818static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
819 ETH_QUEUE rx_queue,
820 PKT_INFO *p_pkt_info);
821static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
822 ETH_QUEUE rx_queue,
823 PKT_INFO *p_pkt_info);
824
825
826static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
827 ETH_QUEUE tx_queue,
828 int tx_desc_num,
829 int tx_buff_size,
830 unsigned int tx_desc_base_addr,
831 unsigned int tx_buff_base_addr);
832
833static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
834 ETH_QUEUE rx_queue,
835 int rx_desc_num,
836 int rx_buff_size,
837 unsigned int rx_desc_base_addr,
838 unsigned int rx_buff_base_addr);
839
840#endif /* MV64460_ETH_ */