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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 343fb990646cc3d552711bff30bda743de392f08 / . / arch / x86 / cpu / ivybridge / gma.h
blob: e7ec649b80e609df1a744a10c06837fedf8be0cc [file] [log] [blame]
Simon Glasseffcf062014-11-14 20:56:36 -0700[diff] [blame]1/*
2 * From Coreboot file of the same name
3 *
4 * Copyright (C) 2012 Chromium OS Authors
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9/* mailbox 0: header */
10__packed struct opregion_header {
11 u8 signature[16];
12 u32 size;
13 u32 version;
14 u8 sbios_version[32];
15 u8 vbios_version[16];
16 u8 driver_version[16];
17 u32 mailboxes;
18 u8 reserved[164];
19};
20
21#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
22#define IGD_OPREGION_VERSION 2
23
24#define IGD_MBOX1 (1 << 0)
25#define IGD_MBOX2 (1 << 1)
26#define IGD_MBOX3 (1 << 2)
27#define IGD_MBOX4 (1 << 3)
28#define IGD_MBOX5 (1 << 4)
29
30#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
31 IGD_MBOX4 | IGD_MBOX5)
32#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
33
34#define SBIOS_VERSION_SIZE 32
35
36/* mailbox 1: public acpi methods */
37__packed struct opregion_mailbox1 {
38 u32 drdy;
39 u32 csts;
40 u32 cevt;
41 u8 reserved1[20];
42 u32 didl[8];
43 u32 cpdl[8];
44 u32 cadl[8];
45 u32 nadl[8];
46 u32 aslp;
47 u32 tidx;
48 u32 chpd;
49 u32 clid;
50 u32 cdck;
51 u32 sxsw;
52 u32 evts;
53 u32 cnot;
54 u32 nrdy;
55 u8 reserved2[60];
56};
57
58/* mailbox 2: software sci interface */
59__packed struct opregion_mailbox2 {
60 u32 scic;
61 u32 parm;
62 u32 dslp;
63 u8 reserved[244];
64};
65
66/* mailbox 3: power conservation */
67__packed struct opregion_mailbox3 {
68 u32 ardy;
69 u32 aslc;
70 u32 tche;
71 u32 alsi;
72 u32 bclp;
73 u32 pfit;
74 u32 cblv;
75 u16 bclm[20];
76 u32 cpfm;
77 u32 epfm;
78 u8 plut[74];
79 u32 pfmb;
80 u32 ccdv;
81 u32 pcft;
82 u8 reserved[94];
83};
84
85#define IGD_BACKLIGHT_BRIGHTNESS 0xff
86#define IGD_INITIAL_BRIGHTNESS 0x64
87
88#define IGD_FIELD_VALID (1 << 31)
89#define IGD_WORD_FIELD_VALID (1 << 15)
90#define IGD_PFIT_STRETCH 6
91
92/* mailbox 4: vbt */
93__packed struct {
94 u8 gvd1[7168];
95} opregion_vbt_t;
96
97/* IGD OpRegion */
98__packed struct igd_opregion {
99 opregion_header_t header;
100 opregion_mailbox1_t mailbox1;
101 opregion_mailbox2_t mailbox2;
102 opregion_mailbox3_t mailbox3;
103 opregion_vbt_t vbt;
104};
105
106/* Intel Video BIOS (Option ROM) */
107__packed struct optionrom_header {
108 u16 signature;
109 u8 size;
110 u8 reserved[21];
111 u16 pcir_offset;
112 u16 vbt_offset;
113};
114
115#define OPROM_SIGNATURE 0xaa55
116
117__packed struct optionrom_pcir {
118 u32 signature;
119 u16 vendor;
120 u16 device;
121 u16 reserved1;
122 u16 length;
123 u8 revision;
124 u8 classcode[3];
125 u16 imagelength;
126 u16 coderevision;
127 u8 codetype;
128 u8 indicator;
129 u16 reserved2;
130};
131
132__packed struct optionrom_vbt {
133 u8 hdr_signature[20];
134 u16 hdr_version;
135 u16 hdr_size;
136 u16 hdr_vbt_size;
137 u8 hdr_vbt_checksum;
138 u8 hdr_reserved;
139 u32 hdr_vbt_datablock;
140 u32 hdr_aim[4];
141 u8 datahdr_signature[16];
142 u16 datahdr_version;
143 u16 datahdr_size;
144 u16 datahdr_datablocksize;
145 u8 coreblock_id;
146 u16 coreblock_size;
147 u16 coreblock_biossize;
148 u8 coreblock_biostype;
149 u8 coreblock_releasestatus;
150 u8 coreblock_hwsupported;
151 u8 coreblock_integratedhw;
152 u8 coreblock_biosbuild[4];
153 u8 coreblock_biossignon[155];
154};
155
156#define VBT_SIGNATURE 0x54425624