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TsiChung Liew536e7da2008-10-22 11:38:21 +00001/*
2 * Configuation settings for the Freescale MCF53017EVB.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew536e7da2008-10-22 11:38:21 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M53017EVB_H
15#define _M53017EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChung Liew536e7da2008-10-22 11:38:21 +000021
22#define CONFIG_MCFUART
23#define CONFIG_SYS_UART_PORT (0)
24#define CONFIG_BAUDRATE 115200
TsiChung Liew536e7da2008-10-22 11:38:21 +000025
26#undef CONFIG_WATCHDOG
27#define CONFIG_WATCHDOG_TIMEOUT 5000
28
29/* Command line configuration */
TsiChung Liew536e7da2008-10-22 11:38:21 +000030#define CONFIG_CMD_CACHE
31#define CONFIG_CMD_DATE
32#define CONFIG_CMD_ELF
TsiChung Liew536e7da2008-10-22 11:38:21 +000033#undef CONFIG_CMD_I2C
TsiChung Liew536e7da2008-10-22 11:38:21 +000034#define CONFIG_CMD_MII
TsiChung Liew536e7da2008-10-22 11:38:21 +000035#define CONFIG_CMD_PING
36#define CONFIG_CMD_REGINFO
37
38#define CONFIG_SYS_UNIFY_CACHE
39
40#define CONFIG_MCFFEC
41#ifdef CONFIG_MCFFEC
TsiChung Liew536e7da2008-10-22 11:38:21 +000042# define CONFIG_MII 1
43# define CONFIG_MII_INIT 1
44# define CONFIG_SYS_DISCOVER_PHY
45# define CONFIG_SYS_RX_ETH_BUFFER 8
TsiChung Liew9e8e9272010-03-10 18:24:07 -060046# define CONFIG_SYS_TX_ETH_BUFFER 8
47# define CONFIG_SYS_FEC_BUF_USE_SRAM
TsiChung Liew536e7da2008-10-22 11:38:21 +000048# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
49# define CONFIG_HAS_ETH1
50
51# define CONFIG_SYS_FEC0_PINMUX 0
52# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53# define CONFIG_SYS_FEC1_PINMUX 0
54# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
55# define MCFFEC_TOUT_LOOP 50000
TsiChung Liew052c0892009-07-08 07:41:24 +000056
57# define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
58
TsiChung Liew536e7da2008-10-22 11:38:21 +000059/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
60# ifndef CONFIG_SYS_DISCOVER_PHY
61# define FECDUPLEX FULL
62# define FECSPEED _100BASET
63# else
64# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
65# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
66# endif
67# endif /* CONFIG_SYS_DISCOVER_PHY */
68#endif
69
70#define CONFIG_MCFRTC
71#undef RTC_DEBUG
72#define CONFIG_SYS_RTC_CNT (0x8000)
73#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
74
75/* Timer */
76#define CONFIG_MCFTMR
77#undef CONFIG_MCFPIT
78
79/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020080#define CONFIG_SYS_I2C
81#define CONFIG_SYS_I2C_FSL
82#define CONFIG_SYS_FSL_I2C_SPEED 80000
83#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
84#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
TsiChung Liew536e7da2008-10-22 11:38:21 +000085#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
86
87#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
88#define CONFIG_UDP_CHECKSUM
89
90#ifdef CONFIG_MCFFEC
TsiChung Liew536e7da2008-10-22 11:38:21 +000091# define CONFIG_IPADDR 192.162.1.2
92# define CONFIG_NETMASK 255.255.255.0
93# define CONFIG_SERVERIP 192.162.1.1
94# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liew536e7da2008-10-22 11:38:21 +000095#endif /* FEC_ENET */
96
97#define CONFIG_HOSTNAME M53017
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "loadaddr=40010000\0" \
101 "u-boot=u-boot.bin\0" \
102 "load=tftp ${loadaddr) ${u-boot}\0" \
103 "upd=run load; run prog\0" \
104 "prog=prot off 0 3ffff;" \
105 "era 0 3ffff;" \
106 "cp.b ${loadaddr} 0 ${filesize};" \
107 "save\0" \
108 ""
109
110#define CONFIG_PRAM 512 /* 512 KB */
TsiChung Liew536e7da2008-10-22 11:38:21 +0000111#define CONFIG_SYS_LONGHELP /* undef to save memory */
112
113#ifdef CONFIG_CMD_KGDB
114# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
115#else
116# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
117#endif
118
119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
120#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
121#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
122#define CONFIG_SYS_LOAD_ADDR 0x40010000
123
TsiChung Liew536e7da2008-10-22 11:38:21 +0000124#define CONFIG_SYS_CLK 80000000
125#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
126
127#define CONFIG_SYS_MBAR 0xFC000000
128
129/*
130 * Low Level Configuration Settings
131 * (address mappings, register initial values, etc.)
132 * You should know what you are doing if you make changes here.
133 */
134/*
135 * Definitions for initial stack pointer and data area (in DPRAM)
136 */
137#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200138#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
TsiChung Liew9e8e9272010-03-10 18:24:07 -0600139#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200140#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000141#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
142
143/*
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
146 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
147 */
148#define CONFIG_SYS_SDRAM_BASE 0x40000000
149#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
150#define CONFIG_SYS_SDRAM_CFG1 0x43711630
151#define CONFIG_SYS_SDRAM_CFG2 0x56670000
TsiChung Liew9e8e9272010-03-10 18:24:07 -0600152#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
TsiChung Liew536e7da2008-10-22 11:38:21 +0000153#define CONFIG_SYS_SDRAM_EMOD 0x80010000
154#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
155
156#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
157#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
158
159#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
160#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
161
162#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
163#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
164
165/*
166 * For booting Linux, the board info and command line data
167 * have to be in the first 8 MB of memory, since this is
168 * the maximum mapped by the Linux kernel during initialization ??
169 */
170#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000171#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000172
173/*-----------------------------------------------------------------------
174 * FLASH organization
175 */
176#define CONFIG_SYS_FLASH_CFI
177#ifdef CONFIG_SYS_FLASH_CFI
178# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liewbbf6bbf2009-06-11 12:50:05 +0000179# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
180# define CONFIG_FLASH_SPANSION_S29WS_N 1
TsiChung Liew4567c7b2009-06-12 11:31:31 +0000181# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
TsiChung Liew536e7da2008-10-22 11:38:21 +0000182# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
183# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
184# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
185# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
186#endif
187
188#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
189
190/* Configuration for environment
191 * Environment is embedded in u-boot in the second sector of the flash
192 */
angelo@sysam.it944ab342015-03-28 11:34:52 +0100193#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
TsiChung Liew536e7da2008-10-22 11:38:21 +0000194#define CONFIG_ENV_SIZE 0x1000
195#define CONFIG_ENV_SECT_SIZE 0x8000
196#define CONFIG_ENV_IS_IN_FLASH 1
197
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200198#define LDS_BOARD_TEXT \
199 . = DEFINED(env_offset) ? env_offset : .; \
200 common/env_embedded.o (.text*)
201
TsiChung Liew536e7da2008-10-22 11:38:21 +0000202/*-----------------------------------------------------------------------
203 * Cache Configuration
204 */
205#define CONFIG_SYS_CACHELINE_SIZE 16
206
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600207#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200208 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600209#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600211#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
212#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
213 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
214 CF_ACR_EN | CF_ACR_SM_ALL)
215#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
216 CF_CACR_DCM_P)
217
TsiChung Liew536e7da2008-10-22 11:38:21 +0000218/*-----------------------------------------------------------------------
219 * Chipselect bank definitions
220 */
221/*
222 * CS0 - NOR Flash
223 * CS1 - Ext SRAM
224 * CS2 - Available
225 * CS3 - Available
226 * CS4 - Available
227 * CS5 - Available
228 */
229#define CONFIG_SYS_CS0_BASE 0
230#define CONFIG_SYS_CS0_MASK 0x00FF0001
231#define CONFIG_SYS_CS0_CTRL 0x00001FA0
232
233#define CONFIG_SYS_CS1_BASE 0xC0000000
234#define CONFIG_SYS_CS1_MASK 0x00070001
235#define CONFIG_SYS_CS1_CTRL 0x00001FA0
236
237#endif /* _M53017EVB_H */