blob: 92a30ab09fc95e44255d9395470eb3d33872f483 [file] [log] [blame]
York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunee52b182012-10-11 07:13:37 +00005 */
6
7/*
8 * T4240 QDS board configuration file
9 */
York Sun1cb19fb2013-06-27 10:48:29 -070010#ifndef __CONFIG_H
11#define __CONFIG_H
12
York Sunee52b182012-10-11 07:13:37 +000013#define CONFIG_T4240QDS
14#define CONFIG_PHYS_64BIT
York Sunee52b182012-10-11 07:13:37 +000015
16#define CONFIG_FSL_SATA_V2
17#define CONFIG_PCIE4
18
19#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20
York Sun1cb19fb2013-06-27 10:48:29 -070021#ifdef CONFIG_RAMBOOT_PBL
22#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
25#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
26#endif
27
28#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
29/* Set 1M boot space */
30#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
31#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
32 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
33#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34#define CONFIG_SYS_NO_FLASH
35#endif
36
37#define CONFIG_SRIO_PCIE_BOOT_MASTER
38#define CONFIG_DDR_ECC
39
York Sunee52b182012-10-11 07:13:37 +000040#include "t4qds.h"
York Sun1cb19fb2013-06-27 10:48:29 -070041
42#ifdef CONFIG_SYS_NO_FLASH
43#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
44#define CONFIG_ENV_IS_NOWHERE
45#endif
46#else
47#define CONFIG_FLASH_CFI_DRIVER
48#define CONFIG_SYS_FLASH_CFI
49#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
50#endif
51
52#if defined(CONFIG_SPIFLASH)
53#define CONFIG_SYS_EXTRA_ENV_RELOC
54#define CONFIG_ENV_IS_IN_SPI_FLASH
55#define CONFIG_ENV_SPI_BUS 0
56#define CONFIG_ENV_SPI_CS 0
57#define CONFIG_ENV_SPI_MAX_HZ 10000000
58#define CONFIG_ENV_SPI_MODE 0
59#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
60#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
61#define CONFIG_ENV_SECT_SIZE 0x10000
62#elif defined(CONFIG_SDCARD)
63#define CONFIG_SYS_EXTRA_ENV_RELOC
64#define CONFIG_ENV_IS_IN_MMC
65#define CONFIG_SYS_MMC_ENV_DEV 0
66#define CONFIG_ENV_SIZE 0x2000
67#define CONFIG_ENV_OFFSET (512 * 1097)
68#elif defined(CONFIG_NAND)
69#define CONFIG_SYS_EXTRA_ENV_RELOC
70#define CONFIG_ENV_IS_IN_NAND
71#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
72#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
73#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
74#define CONFIG_ENV_IS_IN_REMOTE
75#define CONFIG_ENV_ADDR 0xffe20000
76#define CONFIG_ENV_SIZE 0x2000
77#elif defined(CONFIG_ENV_IS_NOWHERE)
78#define CONFIG_ENV_SIZE 0x2000
79#else
80#define CONFIG_ENV_IS_IN_FLASH
81#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
82#define CONFIG_ENV_SIZE 0x2000
83#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
84#endif
85
86#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
87#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
88
89#ifndef __ASSEMBLY__
90unsigned long get_board_sys_clk(void);
91unsigned long get_board_ddr_clk(void);
92#endif
93
94/* EEPROM */
95#define CONFIG_ID_EEPROM
96#define CONFIG_SYS_I2C_EEPROM_NXID
97#define CONFIG_SYS_EEPROM_BUS_NUM 0
98#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
99#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
100
101/*
102 * DDR Setup
103 */
104#define CONFIG_SYS_SPD_BUS_NUM 0
105#define SPD_EEPROM_ADDRESS1 0x51
106#define SPD_EEPROM_ADDRESS2 0x52
107#define SPD_EEPROM_ADDRESS3 0x53
108#define SPD_EEPROM_ADDRESS4 0x54
109#define SPD_EEPROM_ADDRESS5 0x55
110#define SPD_EEPROM_ADDRESS6 0x56
111#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
112#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
113
114/*
115 * IFC Definitions
116 */
117#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
118#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
119 + 0x8000000) | \
120 CSPR_PORT_SIZE_16 | \
121 CSPR_MSEL_NOR | \
122 CSPR_V)
123#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
124#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
125 CSPR_PORT_SIZE_16 | \
126 CSPR_MSEL_NOR | \
127 CSPR_V)
128#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
129/* NOR Flash Timing Params */
130#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
131
132#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
133 FTIM0_NOR_TEADC(0x5) | \
134 FTIM0_NOR_TEAHC(0x5))
135#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
136 FTIM1_NOR_TRAD_NOR(0x1A) |\
137 FTIM1_NOR_TSEQRAD_NOR(0x13))
138#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
139 FTIM2_NOR_TCH(0x4) | \
140 FTIM2_NOR_TWPH(0x0E) | \
141 FTIM2_NOR_TWP(0x1c))
142#define CONFIG_SYS_NOR_FTIM3 0x0
143
144#define CONFIG_SYS_FLASH_QUIET_TEST
145#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
146
147#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
148#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
149#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
150#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
151
152#define CONFIG_SYS_FLASH_EMPTY_INFO
153#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
154 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
155
156#define CONFIG_FSL_QIXIS /* use common QIXIS code */
157#define QIXIS_BASE 0xffdf0000
158#define QIXIS_LBMAP_SWITCH 6
159#define QIXIS_LBMAP_MASK 0x0f
160#define QIXIS_LBMAP_SHIFT 0
161#define QIXIS_LBMAP_DFLTBANK 0x00
162#define QIXIS_LBMAP_ALTBANK 0x04
163#define QIXIS_RST_CTL_RESET 0x83
York Sunc63e1372013-06-25 11:37:48 -0700164#define QIXIS_RST_FORCE_MEM 0x1
York Sun1cb19fb2013-06-27 10:48:29 -0700165#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
166#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
167#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
168#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
169
170#define CONFIG_SYS_CSPR3_EXT (0xf)
171#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
172 | CSPR_PORT_SIZE_8 \
173 | CSPR_MSEL_GPCM \
174 | CSPR_V)
175#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
176#define CONFIG_SYS_CSOR3 0x0
177/* QIXIS Timing parameters for IFC CS3 */
178#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
179 FTIM0_GPCM_TEADC(0x0e) | \
180 FTIM0_GPCM_TEAHC(0x0e))
181#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
182 FTIM1_GPCM_TRAD(0x3f))
183#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
184 FTIM2_GPCM_TCH(0x0) | \
185 FTIM2_GPCM_TWP(0x1f))
186#define CONFIG_SYS_CS3_FTIM3 0x0
187
188/* NAND Flash on IFC */
189#define CONFIG_NAND_FSL_IFC
190#define CONFIG_SYS_NAND_BASE 0xff800000
191#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
192
193#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
194#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
195 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
196 | CSPR_MSEL_NAND /* MSEL = NAND */ \
197 | CSPR_V)
198#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
199
200#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
201 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
202 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
203 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
204 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
205 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
206 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
207
208#define CONFIG_SYS_NAND_ONFI_DETECTION
209
210/* ONFI NAND Flash mode0 Timing Params */
211#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
212 FTIM0_NAND_TWP(0x18) | \
213 FTIM0_NAND_TWCHT(0x07) | \
214 FTIM0_NAND_TWH(0x0a))
215#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
216 FTIM1_NAND_TWBE(0x39) | \
217 FTIM1_NAND_TRR(0x0e) | \
218 FTIM1_NAND_TRP(0x18))
219#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
220 FTIM2_NAND_TREH(0x0a) | \
221 FTIM2_NAND_TWHRE(0x1e))
222#define CONFIG_SYS_NAND_FTIM3 0x0
223
224#define CONFIG_SYS_NAND_DDR_LAW 11
225
226#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
227#define CONFIG_SYS_MAX_NAND_DEVICE 1
228#define CONFIG_MTD_NAND_VERIFY_WRITE
229#define CONFIG_CMD_NAND
230
231#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
232
233#if defined(CONFIG_NAND)
234#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
235#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
236#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
237#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
238#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
239#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
240#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
241#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
242#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
243#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
244#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
245#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
246#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
247#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
248#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
249#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
250#else
251#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
252#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
253#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
254#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
255#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
256#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
257#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
258#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
259#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
260#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
261#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
262#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
263#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
264#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
265#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
266#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
267#endif
268#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
269#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
270#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
271#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
272#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
273#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
274#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
275#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
276
277#if defined(CONFIG_RAMBOOT_PBL)
278#define CONFIG_SYS_RAMBOOT
279#endif
280
281
282/* I2C */
283#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
284#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
285#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
286#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
287
288#define I2C_MUX_CH_DEFAULT 0x8
289#define I2C_MUX_CH_VOL_MONITOR 0xa
290#define I2C_MUX_CH_VSC3316_FS 0xc
291#define I2C_MUX_CH_VSC3316_BS 0xd
292
293/* Voltage monitor on channel 2*/
294#define I2C_VOL_MONITOR_ADDR 0x40
295#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
296#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
297#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
298
299/* VSC Crossbar switches */
300#define CONFIG_VSC_CROSSBAR
301#define VSC3316_FSM_TX_ADDR 0x70
302#define VSC3316_FSM_RX_ADDR 0x71
303
304/*
305 * RapidIO
306 */
307
308/*
309 * for slave u-boot IMAGE instored in master memory space,
310 * PHYS must be aligned based on the SIZE
311 */
312#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
313#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
314#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
315#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
316/*
317 * for slave UCODE and ENV instored in master memory space,
318 * PHYS must be aligned based on the SIZE
319 */
320#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
321#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
322#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
323
324/* slave core release by master*/
325#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
326#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
327
328/*
329 * SRIO_PCIE_BOOT - SLAVE
330 */
331#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
332#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
333#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
334 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
335#endif
336/*
337 * eSPI - Enhanced SPI
338 */
339#define CONFIG_FSL_ESPI
340#define CONFIG_SPI_FLASH
341#define CONFIG_SPI_FLASH_SST
342#define CONFIG_CMD_SF
343#define CONFIG_SF_DEFAULT_SPEED 10000000
344#define CONFIG_SF_DEFAULT_MODE 0
345
346
347/* Qman/Bman */
348#ifndef CONFIG_NOBQFMAN
349#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
350#define CONFIG_SYS_BMAN_NUM_PORTALS 50
351#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
352#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
353#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
354#define CONFIG_SYS_QMAN_NUM_PORTALS 50
355#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
356#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
357#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
358
359#define CONFIG_SYS_DPAA_FMAN
360#define CONFIG_SYS_DPAA_PME
361#define CONFIG_SYS_PMAN
362#define CONFIG_SYS_DPAA_DCE
Minghuan Lian0795eff2013-07-03 18:32:41 +0800363#define CONFIG_SYS_DPAA_RMAN
York Sun1cb19fb2013-06-27 10:48:29 -0700364#define CONFIG_SYS_INTERLAKEN
365
366/* Default address of microcode for the Linux Fman driver */
367#if defined(CONFIG_SPIFLASH)
368/*
369 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
370 * env, so we got 0x110000.
371 */
372#define CONFIG_SYS_QE_FW_IN_SPIFLASH
373#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
374#elif defined(CONFIG_SDCARD)
375/*
376 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
377 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
378 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
379 */
380#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
381#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
382#elif defined(CONFIG_NAND)
383#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
384#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
385#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
386/*
387 * Slave has no ucode locally, it can fetch this from remote. When implementing
388 * in two corenet boards, slave's ucode could be stored in master's memory
389 * space, the address can be mapped from slave TLB->slave LAW->
390 * slave SRIO or PCIE outbound window->master inbound window->
391 * master LAW->the ucode address in master's memory space.
392 */
393#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
394#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
395#else
396#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
397#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
398#endif
399#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
400#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
401#endif /* CONFIG_NOBQFMAN */
402
403#ifdef CONFIG_SYS_DPAA_FMAN
404#define CONFIG_FMAN_ENET
405#define CONFIG_PHYLIB_10G
406#define CONFIG_PHY_VITESSE
407#define CONFIG_PHY_TERANETICS
408#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
409#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
410#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
411#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
412#define FM1_10GEC1_PHY_ADDR 0x0
413#define FM1_10GEC2_PHY_ADDR 0x1
414#define FM2_10GEC1_PHY_ADDR 0x2
415#define FM2_10GEC2_PHY_ADDR 0x3
416#endif
417
418
419/* SATA */
420#ifdef CONFIG_FSL_SATA_V2
421#define CONFIG_LIBATA
422#define CONFIG_FSL_SATA
423
424#define CONFIG_SYS_SATA_MAX_DEVICE 2
425#define CONFIG_SATA1
426#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
427#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
428#define CONFIG_SATA2
429#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
430#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
431
432#define CONFIG_LBA48
433#define CONFIG_CMD_SATA
434#define CONFIG_DOS_PARTITION
435#define CONFIG_CMD_EXT2
436#endif
437
438#ifdef CONFIG_FMAN_ENET
439#define CONFIG_MII /* MII PHY management */
440#define CONFIG_ETHPRIME "FM1@DTSEC1"
441#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
442#endif
443
444/*
445* USB
446*/
447#define CONFIG_CMD_USB
448#define CONFIG_USB_STORAGE
449#define CONFIG_USB_EHCI
450#define CONFIG_USB_EHCI_FSL
451#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
452#define CONFIG_CMD_EXT2
453#define CONFIG_HAS_FSL_DR_USB
454
455#define CONFIG_MMC
456
457#ifdef CONFIG_MMC
458#define CONFIG_FSL_ESDHC
459#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
460#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
461#define CONFIG_CMD_MMC
462#define CONFIG_GENERIC_MMC
463#define CONFIG_CMD_EXT2
464#define CONFIG_CMD_FAT
465#define CONFIG_DOS_PARTITION
466#endif
467
468#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
469
470#define __USB_PHY_TYPE utmi
471
472/*
473 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
474 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
475 * interleaving. It can be cacheline, page, bank, superbank.
476 * See doc/README.fsl-ddr for details.
477 */
478#ifdef CONFIG_PPC_T4240
479#define CTRL_INTLV_PREFERED 3way_4KB
480#else
481#define CTRL_INTLV_PREFERED cacheline
482#endif
483
484#define CONFIG_EXTRA_ENV_SETTINGS \
485 "hwconfig=fsl_ddr:" \
486 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
487 "bank_intlv=auto;" \
488 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
489 "netdev=eth0\0" \
490 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
491 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
492 "tftpflash=tftpboot $loadaddr $uboot && " \
493 "protect off $ubootaddr +$filesize && " \
494 "erase $ubootaddr +$filesize && " \
495 "cp.b $loadaddr $ubootaddr $filesize && " \
496 "protect on $ubootaddr +$filesize && " \
497 "cmp.b $loadaddr $ubootaddr $filesize\0" \
498 "consoledev=ttyS0\0" \
499 "ramdiskaddr=2000000\0" \
500 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
501 "fdtaddr=c00000\0" \
502 "fdtfile=t4240qds/t4240qds.dtb\0" \
503 "bdev=sda3\0" \
504 "c=ffe\0"
505
506#define CONFIG_HVBOOT \
507 "setenv bootargs config-addr=0x60000000; " \
508 "bootm 0x01000000 - 0x00f00000"
509
510#define CONFIG_ALU \
511 "setenv bootargs root=/dev/$bdev rw " \
512 "console=$consoledev,$baudrate $othbootargs;" \
513 "cpu 1 release 0x01000000 - - -;" \
514 "cpu 2 release 0x01000000 - - -;" \
515 "cpu 3 release 0x01000000 - - -;" \
516 "cpu 4 release 0x01000000 - - -;" \
517 "cpu 5 release 0x01000000 - - -;" \
518 "cpu 6 release 0x01000000 - - -;" \
519 "cpu 7 release 0x01000000 - - -;" \
520 "go 0x01000000"
521
522#define CONFIG_LINUX \
523 "setenv bootargs root=/dev/ram rw " \
524 "console=$consoledev,$baudrate $othbootargs;" \
525 "setenv ramdiskaddr 0x02000000;" \
526 "setenv fdtaddr 0x00c00000;" \
527 "setenv loadaddr 0x1000000;" \
528 "bootm $loadaddr $ramdiskaddr $fdtaddr"
529
530#define CONFIG_HDBOOT \
531 "setenv bootargs root=/dev/$bdev rw " \
532 "console=$consoledev,$baudrate $othbootargs;" \
533 "tftp $loadaddr $bootfile;" \
534 "tftp $fdtaddr $fdtfile;" \
535 "bootm $loadaddr - $fdtaddr"
536
537#define CONFIG_NFSBOOTCOMMAND \
538 "setenv bootargs root=/dev/nfs rw " \
539 "nfsroot=$serverip:$rootpath " \
540 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
541 "console=$consoledev,$baudrate $othbootargs;" \
542 "tftp $loadaddr $bootfile;" \
543 "tftp $fdtaddr $fdtfile;" \
544 "bootm $loadaddr - $fdtaddr"
545
546#define CONFIG_RAMBOOTCOMMAND \
547 "setenv bootargs root=/dev/ram rw " \
548 "console=$consoledev,$baudrate $othbootargs;" \
549 "tftp $ramdiskaddr $ramdiskfile;" \
550 "tftp $loadaddr $bootfile;" \
551 "tftp $fdtaddr $fdtfile;" \
552 "bootm $loadaddr $ramdiskaddr $fdtaddr"
553
554#define CONFIG_BOOTCOMMAND CONFIG_LINUX
555
556#ifdef CONFIG_SECURE_BOOT
557#include <asm/fsl_secure_boot.h>
558#endif
559
560#endif /* __CONFIG_H */