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Wolfgang Denkf901a832005-08-06 01:42:58 +02001/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * U-Boot configuration for Embedded Planet EP8248 boards.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkf901a832005-08-06 01:42:58 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_MPC8248
14#define CPU_ID_STR "MPC8248"
15
16#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
17
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018#define CONFIG_SYS_TEXT_BASE 0xFFF00000
19
Wolfgang Denkf901a832005-08-06 01:42:58 +020020#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
21
22/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
23#define CONFIG_ENV_OVERWRITE
24
25/*
26 * Select serial console configuration
27 *
28 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
29 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
30 * for SCC).
31 */
32#define CONFIG_CONS_ON_SMC /* Console is on SMC */
33#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
34#undef CONFIG_CONS_NONE /* It's not on external UART */
35#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
36
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_BCSR 0xFA000000
Wolfgang Denkf901a832005-08-06 01:42:58 +020038
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020039/* Pass open firmware flat device tree */
40#define CONFIG_OF_LIBFDT 1
41#define CONFIG_OF_BOARD_SETUP 1
42
43#define OF_TBCLK (bd->bi_busfreq / 4)
44#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
45
46/* Select ethernet configuration */
Wolfgang Denkf901a832005-08-06 01:42:58 +020047#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
48#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
49#undef CONFIG_ETHER_NONE /* No external Ethernet */
50
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020051#define CONFIG_SYS_CPMFCR_RAMTYPE 0
52#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Wolfgang Denkf901a832005-08-06 01:42:58 +020053
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020054#define CONFIG_HAS_ETH0
55#define CONFIG_ETHER_ON_FCC1 1
Wolfgang Denkf901a832005-08-06 01:42:58 +020056/* - Rx clock is CLK10
57 * - Tx clock is CLK11
58 * - BDs/buffers on 60x bus
59 * - Full duplex
60 */
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020061#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
62#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
Wolfgang Denkf901a832005-08-06 01:42:58 +020063
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020064#define CONFIG_HAS_ETH1
65#define CONFIG_ETHER_ON_FCC2 1
Wolfgang Denkf901a832005-08-06 01:42:58 +020066/* - Rx clock is CLK13
67 * - Tx clock is CLK14
68 * - BDs/buffers on 60x bus
69 * - Full duplex
70 */
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020071#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
72#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Wolfgang Denkf901a832005-08-06 01:42:58 +020073
74#define CONFIG_MII /* MII PHY management */
75#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
76/*
77 * GPIO pins used for bit-banged MII communications
78 */
79#define MDIO_PORT 0 /* Not used - implemented in BCSR */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
82#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
83#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
Wolfgang Denkf901a832005-08-06 01:42:58 +020084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
86 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
Wolfgang Denkf901a832005-08-06 01:42:58 +020087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
89 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
Wolfgang Denkf901a832005-08-06 01:42:58 +020090
91#define MIIDELAY udelay(1)
92
Wolfgang Denkf901a832005-08-06 01:42:58 +020093#ifndef CONFIG_8260_CLKIN
94#define CONFIG_8260_CLKIN 66000000 /* in Hz */
95#endif
96
97#define CONFIG_BAUDRATE 38400
98
Wolfgang Denkf901a832005-08-06 01:42:58 +020099
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500100/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500101 * BOOTP options
102 */
103#define CONFIG_BOOTP_BOOTFILESIZE
104#define CONFIG_BOOTP_BOOTPATH
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107
108
109/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500110 * Command line configuration.
111 */
112#include <config_cmd_default.h>
113
114#define CONFIG_CMD_DHCP
115#define CONFIG_CMD_ECHO
116#define CONFIG_CMD_I2C
117#define CONFIG_CMD_IMMAP
118#define CONFIG_CMD_MII
119#define CONFIG_CMD_PING
120
Wolfgang Denkf901a832005-08-06 01:42:58 +0200121
122#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
123#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
124#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
125
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500126#if defined(CONFIG_CMD_KGDB)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200127#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
128#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
129#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
130#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
131#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
132#endif
133
134#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
135#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
136
137/*
138 * Miscellaneous configurable options
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LONGHELP /* undef to save memory */
142#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500143#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200145#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200147#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
153#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkf901a832005-08-06 01:42:58 +0200160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_FLASH_BASE 0xFF800000
162#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200163#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
165#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_DIRECT_FLASH_TFTP
Wolfgang Denkf901a832005-08-06 01:42:58 +0200168
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500169#if defined(CONFIG_CMD_JFFS2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_JFFS2_FIRST_BANK 0
171#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
172#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
173#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
174#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
175#define CONFIG_SYS_JFFS_CUSTOM_PART
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500176#endif
Wolfgang Denkf901a832005-08-06 01:42:58 +0200177
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500178#if defined(CONFIG_CMD_I2C)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200179#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
181#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500182#endif
Wolfgang Denkf901a832005-08-06 01:42:58 +0200183
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200184#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
186#define CONFIG_SYS_RAMBOOT
Wolfgang Denkf901a832005-08-06 01:42:58 +0200187#endif
188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200190
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200191#define CONFIG_ENV_IS_IN_FLASH
Wolfgang Denkf901a832005-08-06 01:42:58 +0200192
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200193#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200194#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200196#endif /* CONFIG_ENV_IS_IN_FLASH */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_IMMR 0xF0000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200203#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkf901a832005-08-06 01:42:58 +0200206
207/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200209/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_HRCW_SLAVE1 0
211#define CONFIG_SYS_HRCW_SLAVE2 0
212#define CONFIG_SYS_HRCW_SLAVE3 0
213#define CONFIG_SYS_HRCW_SLAVE4 0
214#define CONFIG_SYS_HRCW_SLAVE5 0
215#define CONFIG_SYS_HRCW_SLAVE6 0
216#define CONFIG_SYS_HRCW_SLAVE7 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500222#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200224#endif
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_HID0_INIT 0
227#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_HID2 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_SIUMCR 0x01240200
232#define CONFIG_SYS_SYPCR 0xFFFF0683
233#define CONFIG_SYS_BCR 0x00000000
234#define CONFIG_SYS_SCCR SCCR_DFBRG01
Wolfgang Denkf901a832005-08-06 01:42:58 +0200235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_RMR RMR_CSRE
237#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
238#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
239#define CONFIG_SYS_RCCR 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_MPTPR 0x1300
242#define CONFIG_SYS_PSDMR 0x82672522
243#define CONFIG_SYS_PSRT 0x4B
Wolfgang Denkf901a832005-08-06 01:42:58 +0200244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SDRAM_BASE 0x00000000
246#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
247#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
250#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
251#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
252#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
Wolfgang Denkf901a832005-08-06 01:42:58 +0200253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200255
256#endif /* __CONFIG_H */