blob: b23cb96274d3a8ec7aab0ab34e7683ba7ca77327 [file] [log] [blame]
Heiko Schocheraf895e42011-02-22 08:58:19 +01001/*
Gerlando Falautobae54072012-07-27 05:16:35 +00002 * (C) Copyright 2007-2011
Heiko Schocheraf895e42011-02-22 08:58:19 +01003 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocheraf895e42011-02-22 08:58:19 +01006 */
7
Gerlando Falautobae54072012-07-27 05:16:35 +00008#ifndef __CONFIG_H
9#define __CONFIG_H
Heiko Schocheraf895e42011-02-22 08:58:19 +010010
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
Holger Brunck489337f2011-05-02 22:56:55 +000015
Heiko Schocheraf895e42011-02-22 08:58:19 +010016#define CONFIG_MPC8247
Gerlando Falautob83cf842012-07-30 08:22:30 +000017/* MGCOGE */
18#if defined(CONFIG_MGCOGE)
19#define CONFIG_HOSTNAME mgcoge
20#define CONFIG_KM_BOARD_EXTRA_ENV ""
21
22/* MGCOGE3NE */
23#elif defined(CONFIG_MGCOGE3NE)
Holger Brunck489337f2011-05-02 22:56:55 +000024#define CONFIG_HOSTNAME mgcoge3ne
25#define CONFIG_KM_82XX
Gerlando Falautobae54072012-07-27 05:16:35 +000026#define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0"
Heiko Schocheraf895e42011-02-22 08:58:19 +010027
Gerlando Falautob83cf842012-07-30 08:22:30 +000028#else
29#error ("Board unsupported")
30#endif
31
Heiko Schocheraf895e42011-02-22 08:58:19 +010032#define CONFIG_SYS_TEXT_BASE 0xFE000000
33
34/* include common defines/options for all Keymile boards */
Valentin Longchamp264eaa02011-05-04 01:47:33 +000035#include "km/keymile-common.h"
36#include "km/km-powerpc.h"
Heiko Schocheraf895e42011-02-22 08:58:19 +010037
38#define CONFIG_SYS_SDRAM_BASE 0x00000000
39#define CONFIG_SYS_FLASH_BASE 0xFE000000
40#define CONFIG_SYS_FLASH_SIZE 32
41#define CONFIG_SYS_FLASH_CFI
42#define CONFIG_FLASH_CFI_DRIVER
Gerlando Falautob83cf842012-07-30 08:22:30 +000043
44/* MGCOGE */
45#if defined(CONFIG_MGCOGE)
46#define CONFIG_SYS_MAX_FLASH_BANKS 3
47/* max num of sects on one chip */
48#define CONFIG_SYS_MAX_FLASH_SECT 512
49
50#define CONFIG_SYS_FLASH_BASE_1 0x50000000
51#define CONFIG_SYS_FLASH_SIZE_1 32
52#define CONFIG_SYS_FLASH_BASE_2 0x52000000
53#define CONFIG_SYS_FLASH_SIZE_2 32
54
55#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
56 CONFIG_SYS_FLASH_BASE_1, \
57 CONFIG_SYS_FLASH_BASE_2 }
58#define MTDIDS_DEFAULT "nor3=app"
59
60/*
61 * Bank 1 - 60x bus SDRAM
62 */
63#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
64#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
65
66/* SDRAM initialization values
67*/
68
69#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
70 ORxS_SDAM_MSK) |\
71 ORxS_BPD_8 |\
72 ORxS_ROWST_PBI0_A7 |\
73 ORxS_NUMR_13)
74
75#define CONFIG_SYS_PSDMR ( \
76 PSDMR_SDAM_A14_IS_A5 |\
77 PSDMR_BSMA_A14_A16 |\
78 PSDMR_SDA10_PBI0_A9 |\
79 PSDMR_RFRC_5_CLK |\
80 PSDMR_PRETOACT_2W |\
81 PSDMR_ACTTORW_2W |\
82 PSDMR_LDOTOPRE_1C |\
83 PSDMR_WRC_1C |\
84 PSDMR_CL_2)
85
86/* MGCOGE3NE */
87#elif defined(CONFIG_MGCOGE3NE)
Holger Brunck489337f2011-05-02 22:56:55 +000088#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
89#define CONFIG_SYS_MAX_FLASH_SECT 1024 /*
Heiko Schocheraf895e42011-02-22 08:58:19 +010090 * max num of sects on one
91 * chip
92 */
93
94#define CONFIG_SYS_FLASH_BASE_1 0x50000000
Holger Brunck489337f2011-05-02 22:56:55 +000095#define CONFIG_SYS_FLASH_SIZE_1 128
96
97#define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */
Heiko Schocheraf895e42011-02-22 08:58:19 +010098
99#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
100 CONFIG_SYS_FLASH_BASE_1 }
101
102#define MTDIDS_DEFAULT "nor2=app"
103
Holger Brunck489337f2011-05-02 22:56:55 +0000104/*
105 * Bank 1 - 60x bus SDRAM
Gerlando Falautoc9718212012-07-27 05:16:39 +0000106 * mgcoge3ne has 256MB
107 * mgcoge2ne has 128MB
Holger Brunck489337f2011-05-02 22:56:55 +0000108 */
109#define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */
110#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */
111
Gerlando Falautobae54072012-07-27 05:16:35 +0000112#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
113 ORxS_SDAM_MSK) |\
Holger Brunck489337f2011-05-02 22:56:55 +0000114 ORxS_BPD_4 |\
Gerlando Falauto56249fe2012-07-27 05:16:40 +0000115 ORxS_NUMR_13 |\
116 ORxS_IBID)
Holger Brunck489337f2011-05-02 22:56:55 +0000117
Gerlando Falautobae54072012-07-27 05:16:35 +0000118#define CONFIG_SYS_PSDMR ( \
119 PSDMR_PBI |\
Gerlando Falauto56249fe2012-07-27 05:16:40 +0000120 PSDMR_RFEN |\
Gerlando Falautobae54072012-07-27 05:16:35 +0000121 PSDMR_BSMA_A13_A15 |\
Gerlando Falautobae54072012-07-27 05:16:35 +0000122 PSDMR_RFRC_5_CLK |\
123 PSDMR_PRETOACT_2W |\
124 PSDMR_ACTTORW_2W |\
125 PSDMR_LDOTOPRE_1C |\
Gerlando Falauto56249fe2012-07-27 05:16:40 +0000126 PSDMR_WRC_1C |\
Holger Brunck489337f2011-05-02 22:56:55 +0000127 PSDMR_CL_2)
Gerlando Falautoc9718212012-07-27 05:16:39 +0000128
129#define CONFIG_SYS_SDRAM_LIST { \
130 { .size = 256 << 20, \
131 .or1 = ORxS_ROWST_PBI1_A4, \
132 .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \
133 }, \
134 { .size = 128 << 20, \
135 .or1 = ORxS_ROWST_PBI1_A5, \
136 .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \
137 }, \
138}
Gerlando Falautob83cf842012-07-30 08:22:30 +0000139#endif /* defined(CONFIG_MGCOGE3NE) */
Holger Brunck489337f2011-05-02 22:56:55 +0000140
Heiko Schocheraf895e42011-02-22 08:58:19 +0100141/* include further common stuff for all keymile 82xx boards */
Gerlando Falauto65c7f922012-07-27 05:16:37 +0000142/*
143 * Select serial console configuration
144 *
145 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
146 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
147 * for SCC).
148 */
149#define CONFIG_CONS_ON_SMC /* Console is on SMC */
150#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
151#undef CONFIG_CONS_NONE /* It's not on external UART */
152#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
153#define CONFIG_SYS_SMC_RXBUFLEN 128
154#define CONFIG_SYS_MAXIDLE 10
155
156/*
157 * Select ethernet configuration
158 *
159 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
160 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
161 * SCC, 1-3 for FCC)
162 *
163 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
164 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
165 * must be unset.
166 */
167#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
168#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
169#undef CONFIG_ETHER_NONE /* No external Ethernet */
170
171#define CONFIG_ETHER_INDEX 4
172#define CONFIG_HAS_ETH0
173#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
174
175#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
176
177#ifndef CONFIG_8260_CLKIN
178#define CONFIG_8260_CLKIN 66000000 /* in Hz */
179#endif
180
181#define BOOTFLASH_START 0xFE000000
182
183#define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
184
185#define MTDPARTS_DEFAULT "mtdparts=" \
186 "app:" \
187 "768k(u-boot)," \
188 "128k(env)," \
189 "128k(envred)," \
190 "3072k(free)," \
191 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
192
193/*
194 * Default environment settings
195 */
196#define CONFIG_EXTRA_ENV_SETTINGS \
197 CONFIG_KM_BOARD_EXTRA_ENV \
198 CONFIG_KM_DEF_ENV \
Gerlando Falauto65c7f922012-07-27 05:16:37 +0000199 "unlock=yes\0" \
200 "newenv=" \
201 "prot off 0xFE0C0000 +0x40000 && " \
202 "era 0xFE0C0000 +0x40000\0" \
203 "arch=ppc_82xx\0" \
204 ""
205
206#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
207#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
208#define CONFIG_SYS_RAMBOOT
209#endif
210
211#define CONFIG_SYS_MONITOR_LEN (768 << 10)
212
213#define CONFIG_ENV_IS_IN_FLASH
214
215#ifdef CONFIG_ENV_IS_IN_FLASH
216#define CONFIG_ENV_SECT_SIZE 0x20000
217#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
218 CONFIG_SYS_MONITOR_LEN)
219#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
220
221/* Address and size of Redundant Environment Sector */
222#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
223 CONFIG_ENV_SECT_SIZE)
224#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
225#endif /* CONFIG_ENV_IS_IN_FLASH */
226
227/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +0100228#define CONFIG_SYS_I2C
229#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
230#define CONFIG_SYS_NUM_I2C_BUSES 3
231#define CONFIG_SYS_I2C_MAX_HOPS 1
232#define CONFIG_SYS_I2C_SOFT_SPEED 50000
233#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED
234#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
235#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
236 {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
237 {0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
Gerlando Falauto65c7f922012-07-27 05:16:37 +0000238
Heiko Schocherf3e93612012-10-25 11:07:00 +0200239#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Gerlando Falauto65c7f922012-07-27 05:16:37 +0000240
241/*
242 * Software (bit-bang) I2C driver configuration
243 */
244
245#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
246#define I2C_ACTIVE (iop->pdir |= 0x00010000)
247#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
248#define I2C_READ ((iop->pdat & 0x00010000) != 0)
249#define I2C_SDA(bit) do { \
250 if (bit) \
251 iop->pdat |= 0x00010000; \
252 else \
253 iop->pdat &= ~0x00010000; \
254 } while (0)
255#define I2C_SCL(bit) do { \
256 if (bit) \
257 iop->pdat |= 0x00020000; \
258 else \
259 iop->pdat &= ~0x00020000; \
260 } while (0)
261#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
262
263#ifndef __ASSEMBLY__
264void set_sda(int state);
265void set_scl(int state);
266int get_sda(void);
267int get_scl(void);
268#endif
269
270/* I2C SYSMON (LM75, AD7414 is almost compatible) */
271#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
272#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
273#define CONFIG_SYS_DTT_MAX_TEMP 70
274#define CONFIG_SYS_DTT_LOW_TEMP -30
275#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocherea818db2013-01-29 08:53:15 +0100276#define CONFIG_SYS_DTT_BUS_NUM 2
Gerlando Falauto65c7f922012-07-27 05:16:37 +0000277
278#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
279
280#define CONFIG_SYS_IMMR 0xF0000000
281
282#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
283#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
284#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
285 GENERATED_GBL_DATA_SIZE)
286#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
287
288/* Hard reset configuration word */
289#define CONFIG_SYS_HRCW_MASTER 0x0604b211
290
291/* No slaves */
292#define CONFIG_SYS_HRCW_SLAVE1 0
293#define CONFIG_SYS_HRCW_SLAVE2 0
294#define CONFIG_SYS_HRCW_SLAVE3 0
295#define CONFIG_SYS_HRCW_SLAVE4 0
296#define CONFIG_SYS_HRCW_SLAVE5 0
297#define CONFIG_SYS_HRCW_SLAVE6 0
298#define CONFIG_SYS_HRCW_SLAVE7 0
299
300/* Initial Memory map for Linux */
301#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
302
303#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
304#if defined(CONFIG_CMD_KGDB)
305# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
306#endif
307
308#define CONFIG_SYS_HID0_INIT 0
309#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
310
311#define CONFIG_SYS_HID2 0
312
313#define CONFIG_SYS_SIUMCR 0x4020c200
314#define CONFIG_SYS_SYPCR 0xFFFFFF83
315#define CONFIG_SYS_BCR 0x10000000
316#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
317
318/*
319 *-----------------------------------------------------------------------
320 * RMR - Reset Mode Register 5-5
321 *-----------------------------------------------------------------------
322 * turn on Checkstop Reset Enable
323 */
324#define CONFIG_SYS_RMR 0
325
326/*
327 *-----------------------------------------------------------------------
328 * TMCNTSC - Time Counter Status and Control 4-40
329 *-----------------------------------------------------------------------
330 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
331 * and enable Time Counter
332 */
333#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
334
335/*
336 *-----------------------------------------------------------------------
337 * PISCR - Periodic Interrupt Status and Control 4-42
338 *-----------------------------------------------------------------------
339 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
340 * Periodic timer
341 */
342#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
343
344/*
345 *-----------------------------------------------------------------------
346 * RCCR - RISC Controller Configuration 13-7
347 *-----------------------------------------------------------------------
348 */
349#define CONFIG_SYS_RCCR 0
350
351/*
352 * Init Memory Controller:
353 *
354 * Bank Bus Machine PortSz Device
355 * ---- --- ------- ------ ------
356 * 0 60x GPCM 8 bit FLASH
357 * 1 60x SDRAM 32 bit SDRAM
358 * 3 60x GPCM 8 bit GPIO/PIGGY
359 * 5 60x GPCM 16 bit CFG-Flash
360 *
361 */
362/* Bank 0 - FLASH
363 */
364#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
365 BRx_PS_8 |\
366 BRx_MS_GPCM_P |\
367 BRx_V)
368
369#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
370 ORxG_CSNT |\
371 ORxG_ACS_DIV2 |\
372 ORxG_SCY_5_CLK |\
373 ORxG_TRLX)
374
375#define CONFIG_SYS_MPTPR 0x1800
376
377/*
378 *-----------------------------------------------------------------------------
379 * Address for Mode Register Set (MRS) command
380 *-----------------------------------------------------------------------------
381 */
382#define CONFIG_SYS_MRS_OFFS 0x00000110
383#define CONFIG_SYS_PSRT 0x0e
384
385#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
386 BRx_PS_64 |\
387 BRx_MS_SDRAM_P |\
388 BRx_V)
389
390#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
391
392/*
393 * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
394 */
395#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
396#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
397
398#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
399 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
400
401#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
402 ORxG_CSNT | ORxG_ACS_DIV2 |\
403 ORxG_SCY_3_CLK | ORxG_TRLX)
404
405/*
406 * BFTICU board FPGA on CS4 initialization values
407 */
408#define CONFIG_SYS_FPGA_BASE 0x40000000
409#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
410
411#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
412 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
413
414#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
415 ORxG_CSNT | ORxG_ACS_DIV2 |\
416 ORxG_SCY_3_CLK | ORxG_TRLX)
417
418/*
419 * CFG-Flash on CS5 initialization values
420 */
421#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
422 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
423
424#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
425 CONFIG_SYS_FLASH_SIZE_2) |\
426 ORxG_CSNT | ORxG_ACS_DIV2 |\
427 ORxG_SCY_5_CLK | ORxG_TRLX)
428
429#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
430
431/* pass open firmware flat tree */
432#define CONFIG_FIT 1
433#define CONFIG_OF_LIBFDT 1
434#define CONFIG_OF_BOARD_SETUP 1
435
436#define OF_TBCLK (bd->bi_busfreq / 4)
437#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
Heiko Schocheraf895e42011-02-22 08:58:19 +0100438
Gerlando Falautobae54072012-07-27 05:16:35 +0000439#endif /* __CONFIG_H */