blob: 15b7232fd7bc54a5cc0318197f4e99feda152b10 [file] [log] [blame]
wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2001
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02003 * Stäubli Faverges - <www.staubli.com>
wdenk5b1d7132002-11-03 00:07:02 +00004 * Pierre AUBERT p.aubert@staubli.com
5 * U-Boot port on RPXClassic LF (CLLF_BW31) board
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk5b1d7132002-11-03 00:07:02 +000011 */
12
13#include <common.h>
14#include <i2c.h>
15#include <config.h>
16#include <mpc8xx.h>
Heiko Schocher76756e42009-03-26 07:33:59 +010017#include <net.h>
wdenk5b1d7132002-11-03 00:07:02 +000018
19/* ------------------------------------------------------------------------- */
20
21static long int dram_size (long int, long int *, long int);
22static unsigned char aschex_to_byte (unsigned char *cp);
23
24/* ------------------------------------------------------------------------- */
25
26#define _NOT_USED_ 0xFFFFCC25
27
28const uint sdram_table[] =
29{
30 /*
31 * Single Read. (Offset 00h in UPMA RAM)
32 */
33 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
34 0x3FBFCC27, /* last */
35 _NOT_USED_, _NOT_USED_, _NOT_USED_,
36
37 /*
38 * Burst Read. (Offset 08h in UPMA RAM)
39 */
40 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
41 0x3FBFCC27, /* last */
42 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
43 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
44 _NOT_USED_, _NOT_USED_, _NOT_USED_,
45
46 /*
47 * Single Write. (Offset 18h in UPMA RAM)
48 */
49 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
50 0x3FFFCC27, /* last */
51 _NOT_USED_, _NOT_USED_, _NOT_USED_,
52
53 /*
54 * Burst Write. (Offset 20h in UPMA RAM)
55 */
56 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
57 0x0CFFCC00, 0x33FFCC27, /* last */
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 _NOT_USED_, _NOT_USED_,
61
62 /*
63 * Refresh. (Offset 30h in UPMA RAM)
64 */
65 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
66 0x3FFFCC27, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_,
69
70 /*
71 * Exception. (Offset 3Ch in UPMA RAM)
72 */
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
74};
75
76/* ------------------------------------------------------------------------- */
77
78
79/*
80 * Check Board Identity:
81 */
82
83int checkboard (void)
84{
85 puts ("Board: RPXClassic\n");
86 return (0);
87}
88
89/*-----------------------------------------------------------------------------
90 * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
91 *-----------------------------------------------------------------------------
92 */
Mike Frysingerd8d21e62009-02-16 18:03:14 -050093static void board_get_enetaddr(uchar *enet)
wdenk5b1d7132002-11-03 00:07:02 +000094{
95 int i;
96 char buff[256], *cp;
97
98 /* Initialize I2C */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
wdenk5b1d7132002-11-03 00:07:02 +0000100
101 /* Read 256 bytes in EEPROM */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200102 i2c_read (0x54, 0, 1, (uchar *)buff, 128);
103 i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
wdenk5b1d7132002-11-03 00:07:02 +0000104
105 /* Retrieve MAC address in buffer (key EA) */
106 for (cp = buff;;) {
107 if (cp[0] == 'E' && cp[1] == 'A') {
108 cp += 3;
109 /* Read MAC address */
110 for (i = 0; i < 6; i++, cp += 2) {
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200111 enet[i] = aschex_to_byte ((unsigned char *)cp);
wdenk5b1d7132002-11-03 00:07:02 +0000112 }
113 }
114 /* Scan to the end of the record */
wdenkb2184c32002-11-19 23:01:07 +0000115 while ((*cp != '\n') && (*cp != (char)0xff)) {
wdenk5b1d7132002-11-03 00:07:02 +0000116 cp++;
117 }
118 /* If the next character is a \n, 0 or ff, we are done. */
119 cp++;
wdenkb2184c32002-11-19 23:01:07 +0000120 if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
wdenk5b1d7132002-11-03 00:07:02 +0000121 break;
122 }
123
124#ifdef CONFIG_FEC_ENET
125 /* The MAC address is the same as normal ethernet except the 3rd byte */
126 /* (See the E.P. Planet Core Overview manual */
127 enet[3] |= 0x80;
wdenk5b1d7132002-11-03 00:07:02 +0000128#endif
129
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500130 printf("MAC address = %pM\n", enet);
131}
wdenk5b1d7132002-11-03 00:07:02 +0000132
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500133int misc_init_r(void)
134{
135 uchar enetaddr[6];
136
137 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
138 board_get_enetaddr(enetaddr);
Heiko Schocher76756e42009-03-26 07:33:59 +0100139 eth_setenv_enetaddr("ethaddr", enetaddr);
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500140 }
141
142 return 0;
wdenk5b1d7132002-11-03 00:07:02 +0000143}
144
145void rpxclassic_init (void)
146{
147 /* Enable NVRAM */
148 *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
149
wdenkb2184c32002-11-19 23:01:07 +0000150#ifdef CONFIG_FEC_ENET
151
152 /* Validate the fast ethernet tranceiver */
153 *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
154 *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
155 *((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
156 *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
157#endif
158
wdenk5b1d7132002-11-03 00:07:02 +0000159}
160
161/* ------------------------------------------------------------------------- */
162
Becky Bruce9973e3c2008-06-09 16:03:40 -0500163phys_size_t initdram (int board_type)
wdenk5b1d7132002-11-03 00:07:02 +0000164{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000166 volatile memctl8xx_t *memctl = &immap->im_memctl;
167 long int size10;
168
169 upmconfig (UPMA, (uint *) sdram_table,
170 sizeof (sdram_table) / sizeof (uint));
171
172 /* Refresh clock prescalar */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenk5b1d7132002-11-03 00:07:02 +0000174
175 memctl->memc_mar = 0x00000000;
176
177 /* Map controller banks 1 to the SDRAM bank */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
179 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
wdenk5b1d7132002-11-03 00:07:02 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenk5b1d7132002-11-03 00:07:02 +0000182
183 udelay (200);
184
185 /* perform SDRAM initializsation sequence */
186
187 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
188 udelay (1);
189
190 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
191
192 udelay (1000);
193
194 /* Check Bank 0 Memory Size
195 * try 10 column mode
196 */
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
wdenk5b1d7132002-11-03 00:07:02 +0000199 SDRAM_MAX_SIZE);
200
201 return (size10);
202}
203
204/* ------------------------------------------------------------------------- */
205
206/*
207 * Check memory range for valid RAM. A simple memory test determines
208 * the actually available RAM size between addresses `base' and
209 * `base + maxsize'. Some (not all) hardware errors are detected:
210 * - short between address lines
211 * - short between data lines
212 */
213
214static long int dram_size (long int mamr_value, long int *base, long int maxsize)
215{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000217 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk5b1d7132002-11-03 00:07:02 +0000218
219 memctl->memc_mamr = mamr_value;
220
wdenkc83bf6a2004-01-06 22:38:14 +0000221 return (get_ram_size(base, maxsize));
wdenk5b1d7132002-11-03 00:07:02 +0000222}
wdenkb2184c32002-11-19 23:01:07 +0000223/*-----------------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000224 * aschex_to_byte --
wdenkb2184c32002-11-19 23:01:07 +0000225 *-----------------------------------------------------------------------------
226 */
wdenk5b1d7132002-11-03 00:07:02 +0000227static unsigned char aschex_to_byte (unsigned char *cp)
228{
229 u_char byte, c;
230
231 c = *cp++;
232
233 if ((c >= 'A') && (c <= 'F')) {
234 c -= 'A';
235 c += 10;
236 } else if ((c >= 'a') && (c <= 'f')) {
237 c -= 'a';
238 c += 10;
239 } else {
240 c -= '0';
241 }
242
243 byte = c * 16;
244
245 c = *cp;
246
247 if ((c >= 'A') && (c <= 'F')) {
248 c -= 'A';
249 c += 10;
250 } else if ((c >= 'a') && (c <= 'f')) {
251 c -= 'a';
252 c += 10;
253 } else {
254 c -= '0';
255 }
256
257 byte += c;
258
259 return (byte);
260}