blob: 45f01de820c7fb50f628b5b7bef2c0daec2a2726 [file] [log] [blame]
wdenk4d75a502003-03-25 16:50:56 +00001
2#ifndef _PPC_KERNEL_M8260_PCI_H
3#define _PPC_KERNEL_M8260_PCI_H
4
5#define M8265_PCIBR0 0x101ac
6#define M8265_PCIBR1 0x101b0
7#define M8265_PCIMSK0 0x101c4
8#define M8265_PCIMSK1 0x101c8
9
10/* Bit definitions for PCIBR registers */
11
12#define PCIBR_ENABLE 0x00000001
13
14/* Bit definitions for PCIMSK registers */
15
16#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
17#define PCIMSK_64KB 0xFFFF0000
18#define PCIMSK_128KB 0xFFFE0000
19#define PCIMSK_256KB 0xFFFC0000
20#define PCIMSK_512KB 0xFFF80000
21#define PCIMSK_1MB 0xFFF00000
22#define PCIMSK_2MB 0xFFE00000
23#define PCIMSK_4MB 0xFFC00000
24#define PCIMSK_8MB 0xFF800000
25#define PCIMSK_16MB 0xFF000000
26#define PCIMSK_32MB 0xFE000000
27#define PCIMSK_64MB 0xFC000000
28#define PCIMSK_128MB 0xF8000000
29#define PCIMSK_256MB 0xF0000000
30#define PCIMSK_512MB 0xE0000000
31#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
32
33
34#define M826X_SCCR_PCI_MODE_EN 0x100
35
36
37/*
wdenk8bde7f72003-06-27 21:31:46 +000038 * Outbound ATU registers (3 sets). These registers control how 60x bus (local)
39 * addresses are translated to PCI addresses when the MPC826x is a PCI bus
wdenk4d75a502003-03-25 16:50:56 +000040 * master (initiator).
41 */
42
43#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
44#define POTAR_REG1 0x10818
45#define POTAR_REG2 0x10830
46
47#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
48#define POBAR_REG1 0x10820
49#define POBAR_REG2 0x10838
50
51#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
52#define POCMR_REG1 0x10828
53#define POCMR_REG2 0x10840
54
55/* Bit definitions for POMCR registers */
56
57#define POCMR_MASK_4KB 0x000FFFFF
58#define POCMR_MASK_8KB 0x000FFFFE
59#define POCMR_MASK_16KB 0x000FFFFC
60#define POCMR_MASK_32KB 0x000FFFF8
61#define POCMR_MASK_64KB 0x000FFFF0
62#define POCMR_MASK_128KB 0x000FFFE0
63#define POCMR_MASK_256KB 0x000FFFC0
64#define POCMR_MASK_512KB 0x000FFF80
65#define POCMR_MASK_1MB 0x000FFF00
66#define POCMR_MASK_2MB 0x000FFE00
67#define POCMR_MASK_4MB 0x000FFC00
68#define POCMR_MASK_8MB 0x000FF800
69#define POCMR_MASK_16MB 0x000FF000
70#define POCMR_MASK_32MB 0x000FE000
71#define POCMR_MASK_64MB 0x000FC000
72#define POCMR_MASK_128MB 0x000F8000
73#define POCMR_MASK_256MB 0x000F0000
74#define POCMR_MASK_512MB 0x000E0000
75#define POCMR_MASK_1GB 0x000C0000
76
77#define POCMR_ENABLE 0x80000000
78#define POCMR_PCI_IO 0x40000000
79#define POCMR_PREFETCH_EN 0x20000000
80
81/* Soft PCI reset */
82
83#define PCI_GCR_REG 0x10880
84
85/* Bit definitions for PCI_GCR registers */
86
87#define PCIGCR_PCI_BUS_EN 0x1
88
89/*
wdenk8bde7f72003-06-27 21:31:46 +000090 * Inbound ATU registers (2 sets). These registers control how PCI addresses
wdenk4d75a502003-03-25 16:50:56 +000091 * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
92 */
93
94#define PITAR_REG1 0x108D0
95#define PIBAR_REG1 0x108D8
96#define PICMR_REG1 0x108E0
97#define PITAR_REG0 0x108E8
98#define PIBAR_REG0 0x108F0
99#define PICMR_REG0 0x108F8
100
101/* Bit definitions for PCI Inbound Comparison Mask registers */
102
103#define PICMR_MASK_4KB 0x000FFFFF
104#define PICMR_MASK_8KB 0x000FFFFE
105#define PICMR_MASK_16KB 0x000FFFFC
106#define PICMR_MASK_32KB 0x000FFFF8
107#define PICMR_MASK_64KB 0x000FFFF0
108#define PICMR_MASK_128KB 0x000FFFE0
109#define PICMR_MASK_256KB 0x000FFFC0
110#define PICMR_MASK_512KB 0x000FFF80
111#define PICMR_MASK_1MB 0x000FFF00
112#define PICMR_MASK_2MB 0x000FFE00
113#define PICMR_MASK_4MB 0x000FFC00
114#define PICMR_MASK_8MB 0x000FF800
115#define PICMR_MASK_16MB 0x000FF000
116#define PICMR_MASK_32MB 0x000FE000
117#define PICMR_MASK_64MB 0x000FC000
118#define PICMR_MASK_128MB 0x000F8000
119#define PICMR_MASK_256MB 0x000F0000
120#define PICMR_MASK_512MB 0x000E0000
121#define PICMR_MASK_1GB 0x000C0000
122
123#define PICMR_ENABLE 0x80000000
124#define PICMR_NO_SNOOP_EN 0x40000000
125#define PICMR_PREFETCH_EN 0x20000000
126
127/* PCI error Registers */
128
129#define PCI_ERROR_STATUS_REG 0x10884
130#define PCI_ERROR_MASK_REG 0x10888
131#define PCI_ERROR_CONTROL_REG 0x1088C
132#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
133#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
134#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
135
136/* PCI error Register bit defines */
137
138#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
139#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
140#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
141#define PCI_ERROR_PCI_NO_RSP 0x00000008
142#define PCI_ERROR_PCI_TAR_ABT 0x00000010
143#define PCI_ERROR_PCI_SERR 0x00000020
144#define PCI_ERROR_PCI_PERR_RD 0x00000040
145#define PCI_ERROR_PCI_PERR_WR 0x00000080
146#define PCI_ERROR_I2O_OFQO 0x00000100
147#define PCI_ERROR_I2O_IPQO 0x00000200
148#define PCI_ERROR_IRA 0x00000400
149#define PCI_ERROR_NMI 0x00000800
150#define PCI_ERROR_I2O_DBMC 0x00001000
151
152/*
153 * Register pair used to generate configuration cycles on the PCI bus
154 * and access the MPC826x's own PCI configuration registers.
155 */
156
157#define PCI_CFG_ADDR_REG 0x10900
158#define PCI_CFG_DATA_REG 0x10904
159
160/* Bus parking decides where the bus control sits when idle */
161/* If modifying memory controllers for PCI park on the core */
162
163#define PPC_ACR_BUS_PARK_CORE 0x6
164#define PPC_ACR_BUS_PARK_PCI 0x3
165
166#endif /* _PPC_KERNEL_M8260_PCI_H */