blob: 4aade443fbb93606770bbe55039e3517b860f475 [file] [log] [blame]
stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_VOM405 1 /* ...on a VOM405 board */
39
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
42
43#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
52
53#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
54
55#define CONFIG_MII 1 /* MII PHY management */
56#define CONFIG_PHY_ADDR 0 /* PHY address */
57#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
58
59#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
60 CONFIG_BOOTP_DNS | \
61 CONFIG_BOOTP_DNS2 | \
62 CONFIG_BOOTP_SEND_HOSTNAME )
63
64#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
65 CFG_CMD_DHCP | \
66 CFG_CMD_BSP | \
67 CFG_CMD_PCI | \
68 CFG_CMD_IRQ | \
69 CFG_CMD_ELF | \
70 CFG_CMD_I2C | \
71 CFG_CMD_MII | \
72 CFG_CMD_PING | \
73 CFG_CMD_EEPROM )
74
75/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
76#include <cmd_confdefs.h>
77
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
81
82#undef CONFIG_PRAM /* no "protected RAM" */
83
84/*
85 * Miscellaneous configurable options
86 */
87#define CFG_LONGHELP /* undef to save memory */
88#define CFG_PROMPT "=> " /* Monitor Command Prompt */
89
90#undef CFG_HUSH_PARSER /* use "hush" command parser */
91#ifdef CFG_HUSH_PARSER
92#define CFG_PROMPT_HUSH_PS2 "> "
93#endif
94
95#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
96#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
97#else
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#endif
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103
104#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
105
106#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
107
108#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
109#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
110
111#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
112#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
113#define CFG_BASE_BAUD 691200
114#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
115
116/* The following table includes the supported baudrates */
117#define CFG_BAUDRATE_TABLE \
118 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
119 57600, 115200, 230400, 460800, 921600 }
120
121#define CFG_LOAD_ADDR 0x100000 /* default load address */
122#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
123
124#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
125
126#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
127
128#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
129
130#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
131
132/*-----------------------------------------------------------------------
133 * PCI stuff
134 *-----------------------------------------------------------------------
135 */
136#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
137#define PCI_HOST_FORCE 1 /* configure as pci host */
138#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
139
140#define CONFIG_PCI /* include pci support */
141#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
142#undef CONFIG_PCI_PNP /* do pci plug-and-play */
143 /* resource configuration */
144
145#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
146
147#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
148#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
149#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
150#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
151#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
152#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
153#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
154#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
155#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
156
157/*
158 * For booting Linux, the board info and command line data
159 * have to be in the first 8 MB of memory, since this is
160 * the maximum mapped by the Linux kernel during initialization.
161 */
162#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
163/*-----------------------------------------------------------------------
164 * FLASH organization
165 */
166#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
167
168#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
169#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
170
171#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
172#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
173
174#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
175#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
176#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
177/*
178 * The following defines are added for buggy IOP480 byte interface.
179 * All other boards should use the standard values (CPCI405 etc.)
180 */
181#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
182#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
183#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
184
185#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
186
187#if 0 /* test-only */
188#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
189#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
190#endif
191
192/*-----------------------------------------------------------------------
193 * Start addresses for the final memory configuration
194 * (Set up by the startup code)
195 * Please note that CFG_SDRAM_BASE _must_ start at 0
196 */
197#define CFG_SDRAM_BASE 0x00000000
198#define CFG_FLASH_BASE 0xFFFC0000
199#define CFG_MONITOR_BASE TEXT_BASE
200#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
201#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
202
203#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
204# define CFG_RAMBOOT 1
205#else
206# undef CFG_RAMBOOT
207#endif
208
209/*-----------------------------------------------------------------------
210 * Environment Variable setup
211 */
212#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
213#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
214#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
215 /* total size of a CAT24WC16 is 2048 bytes */
216
217#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
218#define CFG_NVRAM_SIZE 242 /* NVRAM size */
219
220/*-----------------------------------------------------------------------
221 * I2C EEPROM (CAT24WC16) for environment
222 */
223#define CONFIG_HARD_I2C /* I2c with hardware support */
224#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
225#define CFG_I2C_SLAVE 0x7F
226
227#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
228#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
229/* mask of address bits that overflow into the "EEPROM chip address" */
230#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
231#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
232 /* 16 byte page write mode using*/
233 /* last 4 bits of the address */
234#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
235#define CFG_EEPROM_PAGE_WRITE_ENABLE
236
237/*-----------------------------------------------------------------------
238 * Cache Configuration
239 */
240#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
241 /* have only 8kB, 16kB is save here */
242#define CFG_CACHELINE_SIZE 32 /* ... */
243#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
244#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
245#endif
246
247/*-----------------------------------------------------------------------
248 * External Bus Controller (EBC) Setup
249 */
250
251#define CAN_BA 0xF0000000 /* CAN Base Address */
252
253/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
254#define CFG_EBC_PB0AP 0x92015480
255#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
256
257/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
258#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
259#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
260
261/*-----------------------------------------------------------------------
262 * FPGA stuff
263 */
264#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
265#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
266
267/* FPGA program pin configuration */
268#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
269#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
270#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
271#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
272#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
273
274/*-----------------------------------------------------------------------
275 * Definitions for initial stack pointer and data area (in data cache)
276 */
277/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
278#define CFG_TEMP_STACK_OCM 1
279
280/* On Chip Memory location */
281#define CFG_OCM_DATA_ADDR 0xF8000000
282#define CFG_OCM_DATA_SIZE 0x1000
283#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
284#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
285
286#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
287#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
288#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
289
290/*-----------------------------------------------------------------------
291 * Definitions for GPIO setup (PPC405EP specific)
292 *
293 * GPIO0[0] - External Bus Controller BLAST output
294 * GPIO0[1-9] - Instruction trace outputs -> GPIO
295 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
296 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
297 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
298 * GPIO0[24-27] - UART0 control signal inputs/outputs
299 * GPIO0[28-29] - UART1 data signal input/output
300 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
301 */
302/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
303/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
304/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
305/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
306#define CFG_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
307#define CFG_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
308#define CFG_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
309#define CFG_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
310#define CFG_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
311#define CFG_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
312#define CFG_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
313
314/*
315 * Internal Definitions
316 *
317 * Boot Flags
318 */
319#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
320#define BOOTFLAG_WARM 0x02 /* Software reboot */
321
322/*
323 * Default speed selection (cpu_plb_opb_ebc) in mhz.
324 * This value will be set if iic boot eprom is disabled.
325 */
326#if 0
327#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
328#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
329#endif
330#if 0
331#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
332#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
333#endif
334#if 1
335#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
336#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
337#endif
338
339#endif /* __CONFIG_H */