Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 34ded875067306961a684186cf23227b58802b28 / . / configs / mpc8308_p1m_defconfig
blob: cb0da4701fb800a589a5b6fff141b6de5551aa91 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini278b90c2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0xFC000000
Mario Sixff3bb0c2019-01-21 09:17:53 +0100[diff] [blame]3CONFIG_SYS_CLK_FREQ=33333333
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]4CONFIG_MPC83xx=y
5CONFIG_TARGET_MPC8308_P1M=y
Mario Six21c15022019-01-21 09:17:54 +0100[diff] [blame]6CONFIG_SYSTEM_PLL_VCO_DIV_2=y
7CONFIG_SYSTEM_PLL_FACTOR_4_1=y
8CONFIG_CORE_PLL_RATIO_3_1=y
9CONFIG_BOOT_MEMORY_SPACE_LOW=y
10CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
Mario Six30915ab2019-01-21 09:17:57 +0100[diff] [blame]11CONFIG_BAT0=y
12CONFIG_BAT0_NAME="DDR"
13CONFIG_BAT0_BASE=0x00000000
14CONFIG_BAT0_LENGTH_128_MBYTES=y
15CONFIG_BAT0_ACCESS_RW=y
16CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
17CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
18CONFIG_BAT0_USER_MODE_VALID=y
19CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
20CONFIG_BAT1=y
21CONFIG_BAT1_NAME="IMMRBAR"
22CONFIG_BAT1_BASE=0xE0000000
23CONFIG_BAT1_LENGTH_8_MBYTES=y
24CONFIG_BAT1_ACCESS_RW=y
25CONFIG_BAT1_ICACHE_INHIBITED=y
26CONFIG_BAT1_ICACHE_GUARDED=y
27CONFIG_BAT1_DCACHE_INHIBITED=y
28CONFIG_BAT1_DCACHE_GUARDED=y
29CONFIG_BAT1_USER_MODE_VALID=y
30CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
31CONFIG_BAT2=y
32CONFIG_BAT2_NAME="FLASH"
33CONFIG_BAT2_BASE=0xFC000000
34CONFIG_BAT2_LENGTH_8_MBYTES=y
35CONFIG_BAT2_ACCESS_RW=y
36CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
37CONFIG_BAT2_DCACHE_INHIBITED=y
38CONFIG_BAT2_DCACHE_GUARDED=y
39CONFIG_BAT2_USER_MODE_VALID=y
40CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
41CONFIG_BAT3=y
42CONFIG_BAT3_NAME="STACKINDCACHE"
43CONFIG_BAT3_BASE=0xE6000000
44CONFIG_BAT3_ACCESS_RW=y
45CONFIG_BAT3_USER_MODE_VALID=y
46CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
Mario Six9c5df7a2019-01-21 09:17:58 +0100[diff] [blame]47CONFIG_LBLAW0=y
48CONFIG_LBLAW0_BASE=0xFC000000
49CONFIG_LBLAW0_NAME="FLASH"
50CONFIG_LBLAW0_LENGTH_64_MBYTES=y
51CONFIG_LBLAW1=y
52CONFIG_LBLAW1_BASE=0xFBFF0000
53CONFIG_LBLAW1_NAME="SJA1000"
54CONFIG_LBLAW1_LENGTH_32_KBYTES=y
55CONFIG_LBLAW2=y
56CONFIG_LBLAW2_BASE=0xFBFF8000
57CONFIG_LBLAW2_NAME="CPLD"
58CONFIG_LBLAW2_LENGTH_32_KBYTES=y
Tom Rini344a0e42019-05-26 14:45:25 -0400[diff] [blame]59CONFIG_ELBC_BR0_OR0=y
60CONFIG_BR0_OR0_NAME="FLASH"
61CONFIG_BR0_OR0_BASE=0xFC000000
62CONFIG_BR0_PORTSIZE_16BIT=y
63CONFIG_OR0_AM_64_MBYTES=y
64CONFIG_OR0_XAM_SET=y
65CONFIG_OR0_SCY_4=y
66CONFIG_OR0_CSNT_EARLIER=y
67CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
68CONFIG_OR0_XACS_EXTENDED=y
69CONFIG_OR0_TRLX_RELAXED=y
70CONFIG_OR0_EHTR_8_CYCLE=y
71CONFIG_ELBC_BR1_OR1=y
72CONFIG_BR1_OR1_NAME="SJA1000"
73CONFIG_BR1_OR1_BASE=0xFBFF0000
74CONFIG_OR1_SCY_5=y
75CONFIG_OR1_EHTR_1_CYCLE=y
76CONFIG_ELBC_BR2_OR2=y
77CONFIG_BR2_OR2_NAME="CPLD"
78CONFIG_BR2_OR2_BASE=0xFBFF8000
79CONFIG_OR2_SCY_4=y
80CONFIG_OR2_EHTR_1_CYCLE=y
Mario Sixbe5abb02019-01-21 09:18:09 +0100[diff] [blame]81CONFIG_HID0_FINAL_EMCP=y
82CONFIG_HID0_FINAL_DPM=y
83CONFIG_HID0_FINAL_ICE=y
84CONFIG_HID2_HBE=y
Mario Sixba463c12019-01-21 09:18:11 +0100[diff] [blame]85CONFIG_SICR_ESDHC_A_GPIO=y
86CONFIG_SICR_ESDHC_B_GPIO=y
87CONFIG_SICR_ESDHC_C_GTM=y
88CONFIG_SICR_GPIO_A_TSEC2=y
89CONFIG_SICR_GPIO_B_TSEC2=y
90CONFIG_SICR_IEEE1588_A_GPIO=y
91CONFIG_SICR_GTM_GPIO=y
92CONFIG_SICR_GPIOSEL_IEEE1588=y
Mario Six73df96a2019-01-21 09:18:12 +0100[diff] [blame]93CONFIG_ACR_PIPE_DEP_4=y
94CONFIG_ACR_RPTCNT_4=y
Mario Sixe35012e2019-01-21 09:18:13 +0100[diff] [blame]95CONFIG_SPCR_TSECEP_3=y
Tom Rini344a0e42019-05-26 14:45:25 -0400[diff] [blame]96CONFIG_LCRR_DBYP_PLL_BYPASSED=y
97CONFIG_LCRR_CLKDIV_2=y
Simon Glass73223f02016-02-22 22:55:43 -0700[diff] [blame]98CONFIG_OF_BOARD_SETUP=y
99CONFIG_OF_STDOUT_VIA_ALIAS=y
Heiko Schocherbb597c02016-06-07 08:31:14 +0200[diff] [blame]100CONFIG_BOOTDELAY=5
Tom Riniadad96e2016-04-21 21:37:19 -0400[diff] [blame]101CONFIG_HUSH_PARSER=y
Adam Fordd021e942018-02-06 07:58:59 -0600[diff] [blame]102# CONFIG_AUTO_COMPLETE is not set
Tuomas Tynkkynenad12dc12017-10-08 21:48:01 +0300[diff] [blame]103CONFIG_CMD_IMLS=y
Tom Rini78d1e1d2016-04-22 16:41:25 -0400[diff] [blame]104CONFIG_CMD_I2C=y
Simon Glass6500ec72017-08-04 16:34:34 -0600[diff] [blame]105CONFIG_CMD_PCI=y
Joe Hershbergeref0f2f52015-06-22 16:15:30 -0500[diff] [blame]106# CONFIG_CMD_SETEXPR is not set
Tom Rini78d1e1d2016-04-22 16:41:25 -0400[diff] [blame]107CONFIG_CMD_DHCP=y
Tom Rini89cb2b52016-04-24 17:29:26 -0400[diff] [blame]108CONFIG_CMD_MII=y
Tom Rini78d1e1d2016-04-22 16:41:25 -0400[diff] [blame]109CONFIG_CMD_PING=y
Tom Rini8728c972017-03-13 13:48:42 -0400[diff] [blame]110# CONFIG_MMC is not set
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900[diff] [blame]111CONFIG_MTD_NOR_FLASH=y
Adam Ford2fe88d42018-10-14 15:10:50 -0500[diff] [blame]112CONFIG_FLASH_CFI_DRIVER=y
113CONFIG_SYS_FLASH_PROTECTION=y
114CONFIG_SYS_FLASH_CFI=y
Mario Sixa8ca5c82018-04-27 14:52:21 +0200[diff] [blame]115CONFIG_PHY_MARVELL=y
Adam Fordd7869b22018-07-20 23:03:57 -0500[diff] [blame]116CONFIG_MII=y
Mario Six17151052018-03-28 14:38:18 +0200[diff] [blame]117CONFIG_TSEC_ENET=y
Thomas Chou9e390032015-11-19 21:48:14 +0800[diff] [blame]118CONFIG_SYS_NS16550=y
Simon Glass69e173e2016-02-22 22:55:42 -0700[diff] [blame]119CONFIG_OF_LIBFDT=y