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wdenkda93ed82004-09-29 11:02:56 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
26#include <mpc8xx.h>
27#include "fpga.h"
28
29/* ------------------------------------------------------------------------- */
30
31static long int dram_size (long int, long int *, long int);
32unsigned long flash_init (void);
33
34/* ------------------------------------------------------------------------- */
35
36#define _NOT_USED_ 0xFFFFCC25
37
38const uint sdram_table[] = {
39 /*
40 * Single Read. (Offset 00h in UPMA RAM)
41 */
42 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
43 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
44
45 /*
46 * Burst Read. (Offset 08h in UPMA RAM)
47 */
48 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
49 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
51 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
52
53 /*
54 * Single Write. (Offset 18h in UPMA RAM)
55 */
56 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58
59 /*
60 * Burst Write. (Offset 20h in UPMA RAM)
61 */
62 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
63 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66
67 /*
68 * Refresh. (Offset 30h in UPMA RAM)
69 * (Initialization code at 0x36)
70 */
71 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
72 _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
73 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
74
75 /*
76 * Exception. (Offset 3Ch in UPMA RAM)
77 */
78 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
79};
80
81/* ------------------------------------------------------------------------- */
82
83
84/*
85 * Check Board Identity:
86 */
87
88int checkboard (void)
89{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000090 char buf[64];
91 int i;
92 int l = getenv_f("serial#", buf, sizeof(buf));
wdenkda93ed82004-09-29 11:02:56 +000093
94 puts ("Board QUANTUM, Serial No: ");
95
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000096 for (i = 0; i < l; ++i) {
97 if (buf[i] == ' ')
wdenkda93ed82004-09-29 11:02:56 +000098 break;
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000099 putc (buf[i]);
wdenkda93ed82004-09-29 11:02:56 +0000100 }
101 putc ('\n');
102 return (0); /* success */
103}
104
105/* ------------------------------------------------------------------------- */
106
Becky Bruce9973e3c2008-06-09 16:03:40 -0500107phys_size_t initdram (int board_type)
wdenkda93ed82004-09-29 11:02:56 +0000108{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkda93ed82004-09-29 11:02:56 +0000110 volatile memctl8xx_t *memctl = &immap->im_memctl;
111 long int size9;
112
113 upmconfig (UPMA, (uint *) sdram_table,
114 sizeof (sdram_table) / sizeof (uint));
115
116 /* Refresh clock prescalar */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkda93ed82004-09-29 11:02:56 +0000118
119 memctl->memc_mar = 0x00000088;
120
121 /* Map controller banks 1 to the SDRAM bank */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
123 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
wdenkda93ed82004-09-29 11:02:56 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenkda93ed82004-09-29 11:02:56 +0000126
127 udelay (200);
128
129 /* perform SDRAM initializsation sequence */
130
131 memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
132 udelay (1);
133
134 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
135
136 udelay (1000);
137
138 /* Check Bank 0 Memory Size,
139 * 9 column mode
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
wdenkda93ed82004-09-29 11:02:56 +0000142 SDRAM_MAX_SIZE);
143 /*
144 * Final mapping:
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkda93ed82004-09-29 11:02:56 +0000147 udelay (1000);
148
149 return (size9);
150}
151
152/* ------------------------------------------------------------------------- */
153
154/*
155 * Check memory range for valid RAM. A simple memory test determines
156 * the actually available RAM size between addresses `base' and
157 * `base + maxsize'. Some (not all) hardware errors are detected:
158 * - short between address lines
159 * - short between data lines
160 */
161
162static long int dram_size (long int mamr_value, long int *base,
163 long int maxsize)
164{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkda93ed82004-09-29 11:02:56 +0000166 volatile memctl8xx_t *memctl = &immap->im_memctl;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200167 volatile ulong *addr;
wdenkda93ed82004-09-29 11:02:56 +0000168 ulong cnt, val, size;
169 ulong save[32]; /* to make test non-destructive */
170 unsigned char i = 0;
171
172 memctl->memc_mamr = mamr_value;
173
174 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200175 addr = (volatile ulong *)(base + cnt); /* pointer arith! */
wdenkda93ed82004-09-29 11:02:56 +0000176
177 save[i++] = *addr;
178 *addr = ~cnt;
179 }
180
181 /* write 0 to base address */
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200182 addr = (volatile ulong *)base;
wdenkda93ed82004-09-29 11:02:56 +0000183 save[i] = *addr;
184 *addr = 0;
185
186 /* check at base address */
187 if ((val = *addr) != 0) {
188 /* Restore the original data before leaving the function.
189 */
190 *addr = save[i];
191 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
192 addr = (volatile ulong *) base + cnt;
193 *addr = save[--i];
194 }
195 return (0);
196 }
197
198 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200199 addr = (volatile ulong *)(base + cnt); /* pointer arith! */
wdenkda93ed82004-09-29 11:02:56 +0000200
201 val = *addr;
202 *addr = save[--i];
203
204 if (val != (~cnt)) {
205 size = cnt * sizeof (long);
206 /* Restore the original data before returning
207 */
208 for (cnt <<= 1; cnt <= maxsize / sizeof (long);
209 cnt <<= 1) {
210 addr = (volatile ulong *) base + cnt;
211 *addr = save[--i];
212 }
213 return (size);
214 }
215 }
216 return (maxsize);
217}
218
219/*
220 * Miscellaneous intialization
221 */
222int misc_init_r (void)
223{
224 char *fpga_data_str = getenv ("fpgadata");
225 char *fpga_size_str = getenv ("fpgasize");
226 void *fpga_data;
227 int fpga_size;
228 int status;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkda93ed82004-09-29 11:02:56 +0000230 volatile memctl8xx_t *memctl = &immap->im_memctl;
231 int flash_size;
232
233 /* Remap FLASH according to real size */
234 flash_size = flash_init ();
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
236 memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
wdenkda93ed82004-09-29 11:02:56 +0000237
238 if (fpga_data_str && fpga_size_str) {
239 fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
240 fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
241
242 status = fpga_boot (fpga_data, fpga_size);
243 if (status != 0) {
244 printf ("\nFPGA: Booting failed ");
245 switch (status) {
246 case ERROR_FPGA_PRG_INIT_LOW:
247 printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
248 break;
249 case ERROR_FPGA_PRG_INIT_HIGH:
250 printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
251 break;
252 case ERROR_FPGA_PRG_DONE:
253 printf ("(Timeout: DONE not high after programming FPGA)\n ");
254 break;
255 }
256 }
257 }
258 return 0;
259}