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Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -04001/*
2 * (C) Copyright 2010
3 * ISEE 2007 SL, <www.iseebcn.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23#include <asm/sizes.h>
24
25/*
26 * High Level Configuration Options
27 */
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -040028#define CONFIG_OMAP 1 /* in a TI OMAP core */
29#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -040030#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */
31
32#define CONFIG_SDRC /* The chip has SDRC controller */
33
34#include <asm/arch/cpu.h>
35#include <asm/arch/omap3.h>
36
37/*
38 * Display CPU and Board information
39 */
40#define CONFIG_DISPLAY_CPUINFO 1
41#define CONFIG_DISPLAY_BOARDINFO 1
42
43/* Clock Defines */
44#define V_OSCK 26000000 /* Clock output from T2 */
45#define V_SCLK (V_OSCK >> 1)
46
47#define CONFIG_MISC_INIT_R
48
49#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
50#define CONFIG_SETUP_MEMORY_TAGS 1
51#define CONFIG_INITRD_TAG 1
52#define CONFIG_REVISION_TAG 1
53
Grant Likely2fa8ca92011-03-28 09:59:07 +000054#define CONFIG_OF_LIBFDT 1
55
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -040056/*
57 * NS16550 Configuration
58 */
59
60#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
61
62#define CONFIG_SYS_NS16550
63#define CONFIG_SYS_NS16550_SERIAL
64#define CONFIG_SYS_NS16550_REG_SIZE (-4)
65#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
66
67/* select serial console configuration */
68#define CONFIG_CONS_INDEX 3
69#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
70#define CONFIG_SERIAL3 3
71
72/* allow to overwrite serial and ethaddr */
73#define CONFIG_ENV_OVERWRITE
74#define CONFIG_BAUDRATE 115200
75#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Enric Balletbo i Serraac657c42010-11-04 15:34:37 -040076#define CONFIG_GENERIC_MMC 1
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -040077#define CONFIG_MMC 1
Enric Balletbo i Serraac657c42010-11-04 15:34:37 -040078#define CONFIG_OMAP_HSMMC 1
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -040079#define CONFIG_DOS_PARTITION 1
80
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -040081/* USB */
82#define CONFIG_MUSB_UDC 1
83#define CONFIG_USB_OMAP3 1
84#define CONFIG_TWL4030_USB 1
85
86/* USB device configuration */
87#define CONFIG_USB_DEVICE 1
88#define CONFIG_USB_TTY 1
89#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
90
91/* Change these to suit your needs */
92#define CONFIG_USBD_VENDORID 0x0451
93#define CONFIG_USBD_PRODUCTID 0x5678
94#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
95#define CONFIG_USBD_PRODUCT_NAME "IGEP"
96
97/* commands to include */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_CACHE
101#define CONFIG_CMD_EXT2 /* EXT2 Support */
102#define CONFIG_CMD_FAT /* FAT support */
103#define CONFIG_CMD_I2C /* I2C serial bus support */
104#define CONFIG_CMD_MMC /* MMC support */
105#define CONFIG_CMD_ONENAND /* ONENAND support */
106#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
107#define CONFIG_MTD_DEVICE
108
109#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
Enric Balletbo i Serra84c611d2010-11-29 16:30:47 -0500110#undef CONFIG_CMD_NFS /* nfs */
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -0400111#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
112#undef CONFIG_CMD_IMLS /* List all found images */
113
114#define CONFIG_SYS_NO_FLASH
115#define CONFIG_HARD_I2C 1
116#define CONFIG_SYS_I2C_SPEED 100000
117#define CONFIG_SYS_I2C_SLAVE 1
118#define CONFIG_SYS_I2C_BUS 0
119#define CONFIG_SYS_I2C_BUS_SELECT 1
120#define CONFIG_DRIVER_OMAP34XX_I2C 1
121
122/*
123 * TWL4030
124 */
125#define CONFIG_TWL4030_POWER 1
126
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -0400127#define CONFIG_BOOTDELAY 3
128
129#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbo i Serra30f34132011-04-19 09:17:11 -0400130 "usbtty=cdc_acm\0" \
131 "loadaddr=0x82000000\0" \
132 "usbtty=cdc_acm\0" \
133 "console=ttyS2,115200n8\0" \
134 "mpurate=500\0" \
135 "vram=12M\0" \
136 "dvimode=1024x768MR-16@60\0" \
137 "defaultdisplay=dvi\0" \
138 "mmcdev=0\0" \
139 "mmcroot=/dev/mmcblk0p2 rw\0" \
140 "mmcrootfstype=ext3 rootwait\0" \
141 "nandroot=/dev/mtdblock4 rw\0" \
142 "nandrootfstype=jffs2\0" \
143 "mmcargs=setenv bootargs console=${console} " \
144 "mpurate=${mpurate} " \
145 "vram=${vram} " \
146 "omapfb.mode=dvi:${dvimode} " \
147 "omapfb.debug=y " \
148 "omapdss.def_disp=${defaultdisplay} " \
149 "root=${mmcroot} " \
150 "rootfstype=${mmcrootfstype}\0" \
151 "nandargs=setenv bootargs console=${console} " \
152 "mpurate=${mpurate} " \
153 "vram=${vram} " \
154 "omapfb.mode=dvi:${dvimode} " \
155 "omapfb.debug=y " \
156 "omapdss.def_disp=${defaultdisplay} " \
157 "root=${nandroot} " \
158 "rootfstype=${nandrootfstype}\0" \
159 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
160 "bootscript=echo Running bootscript from mmc ...; " \
161 "source ${loadaddr}\0" \
162 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
163 "mmcboot=echo Booting from mmc ...; " \
164 "run mmcargs; " \
165 "bootm ${loadaddr}\0" \
166 "nandboot=echo Booting from onenand ...; " \
167 "run nandargs; " \
168 "onenand read ${loadaddr} 280000 400000; " \
169 "bootm ${loadaddr}\0" \
170
171#define CONFIG_BOOTCOMMAND \
172 "if mmc rescan ${mmcdev}; then " \
173 "if run loadbootscript; then " \
174 "run bootscript; " \
175 "else " \
176 "if run loaduimage; then " \
177 "run mmcboot; " \
178 "else run nandboot; " \
179 "fi; " \
180 "fi; " \
181 "else run nandboot; fi"
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -0400182
183#define CONFIG_AUTO_COMPLETE 1
184
185/*
186 * Miscellaneous configurable options
187 */
188#define CONFIG_SYS_LONGHELP /* undef to save memory */
189#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
190#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
191#define CONFIG_SYS_PROMPT "U-Boot # "
192#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
193/* Print Buffer Size */
194#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
195 sizeof(CONFIG_SYS_PROMPT) + 16)
196#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
197/* Boot Argument Buffer Size */
198#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
199
200#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
201 /* works on */
202#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
203 0x01F00000) /* 31MB */
204
205#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
206 /* load address */
207
208#define CONFIG_SYS_MONITOR_LEN (256 << 10)
209
210/*
211 * OMAP3 has 12 GP timers, they can be driven by the system clock
212 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
213 * This rate is divided by a local divisor.
214 */
215#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
216#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
217#define CONFIG_SYS_HZ 1000
218
219/*
220 * Stack sizes
221 *
222 * The stack sizes are set up in start.S using the settings below
223 */
224#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
225
226/*
227 * Physical Memory Map
228 *
229 */
230#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
231#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
232#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
233#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
234
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -0400235/*
236 * FLASH and environment organization
237 */
238
239#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
240
241#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
242
243#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
244
245#define CONFIG_ENV_IS_IN_ONENAND 1
246#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
247#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
248
249/*
250 * Size of malloc() pool
251 */
252#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -0400253
254#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Steve Sakoman31bfcf12010-10-27 05:04:30 -0700255#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
256#define CONFIG_SYS_INIT_RAM_SIZE 0x800
257#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
258 CONFIG_SYS_INIT_RAM_SIZE - \
259 GENERATED_GBL_DATA_SIZE)
Enric Balletbo i Serra1a832dc2010-10-14 16:57:39 -0400260
261#endif /* __CONFIG_H */