| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
| Stelian Pop | c9e798d | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9RLEK board. |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| Xu, Hong | 21d671d | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 13 | #include <asm/hardware.h> |
| 14 | |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 15 | /* ARM asynchronous clock */ |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 16 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 17 | #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 18 | |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 19 | /* SDRAM */ |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 20 | #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 21 | #define CFG_SYS_SDRAM_SIZE 0x04000000 |
| Xu, Hong | 21d671d | 2011-08-01 03:56:53 +0000 | [diff] [blame] | 22 | |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 23 | #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) |
| 24 | #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 25 | |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 26 | /* NAND flash */ |
| Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 27 | #ifdef CONFIG_CMD_NAND |
| Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 28 | #define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 29 | /* our ALE is AD21 */ |
| Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 30 | #define CFG_SYS_NAND_MASK_ALE (1 << 21) |
| Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 31 | /* our CLE is AD22 */ |
| Tom Rini | 4e59094 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 32 | #define CFG_SYS_NAND_MASK_CLE (1 << 22) |
| 33 | #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 |
| 34 | #define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17 |
| Wolfgang Denk | 2eb99ca | 2009-07-18 21:52:24 +0200 | [diff] [blame] | 35 | |
| Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 36 | #endif |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 37 | |
| Stelian Pop | 2118ebb | 2008-05-08 18:52:25 +0200 | [diff] [blame] | 38 | #endif |