blob: bd62aab9f34b9567c43b65e986bc4d1339b09c4a [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * MPC8560 FCC Fast Ethernet
3 * Copyright (c) 2003 Motorola,Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
7 *
8 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * MPC8560 FCC Fast Ethernet
32 * Basic ET HW initialization and packet RX/TX routines
33 *
34 * This code will not perform the IO port configuration. This should be
35 * done in the iop_conf_t structure specific for the board.
36 *
37 * TODO:
38 * add a PHY driver to do the negotiation
39 * reflect negotiation results in FPSMR
40 * look for ways to configure the board specific stuff elsewhere, eg.
41 * config_xxx.h or the board directory
42 */
43
44#include <common.h>
45#include <malloc.h>
46#include <asm/cpm_85xx.h>
47#include <command.h>
48#include <config.h>
49#include <net.h>
50
Jon Loeliger44312832007-07-09 19:06:00 -050051#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020052#include <miiphy.h>
53#endif
54
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050055#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +000056
Jon Loeliger44312832007-07-09 19:06:00 -050057#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \
wdenk42d1f032003-10-15 23:53:47 +000058 defined(CONFIG_NET_MULTI)
59
60static struct ether_fcc_info_s
61{
62 int ether_index;
63 int proff_enet;
64 ulong cpm_cr_enet_sblock;
65 ulong cpm_cr_enet_page;
66 ulong cmxfcr_mask;
67 ulong cmxfcr_value;
68}
69 ether_fcc_info[] =
70{
71#ifdef CONFIG_ETHER_ON_FCC1
72{
73 0,
74 PROFF_FCC1,
75 CPM_CR_FCC1_SBLOCK,
76 CPM_CR_FCC1_PAGE,
77 CFG_CMXFCR_MASK1,
78 CFG_CMXFCR_VALUE1
79},
80#endif
81
82#ifdef CONFIG_ETHER_ON_FCC2
83{
84 1,
85 PROFF_FCC2,
86 CPM_CR_FCC2_SBLOCK,
87 CPM_CR_FCC2_PAGE,
88 CFG_CMXFCR_MASK2,
89 CFG_CMXFCR_VALUE2
90},
91#endif
92
93#ifdef CONFIG_ETHER_ON_FCC3
94{
95 2,
96 PROFF_FCC3,
97 CPM_CR_FCC3_SBLOCK,
98 CPM_CR_FCC3_PAGE,
99 CFG_CMXFCR_MASK3,
100 CFG_CMXFCR_VALUE3
101},
102#endif
103};
104
105/*---------------------------------------------------------------------*/
106
107/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
108#define PKT_MAXDMA_SIZE 1520
109
110/* The FCC stores dest/src/type, data, and checksum for receive packets. */
111#define PKT_MAXBUF_SIZE 1518
112#define PKT_MINBUF_SIZE 64
113
114/* Maximum input buffer size. Must be a multiple of 32. */
115#define PKT_MAXBLR_SIZE 1536
116
117#define TOUT_LOOP 1000000
118
119#define TX_BUF_CNT 2
120
121static uint rxIdx; /* index of the current RX buffer */
122static uint txIdx; /* index of the current TX buffer */
123
124/*
125 * FCC Ethernet Tx and Rx buffer descriptors.
126 * Provide for Double Buffering
127 * Note: PKTBUFSRX is defined in net.h
128 */
129
130typedef volatile struct rtxbd {
131 cbd_t rxbd[PKTBUFSRX];
132 cbd_t txbd[TX_BUF_CNT];
133} RTXBD;
134
135/* Good news: the FCC supports external BDs! */
136#ifdef __GNUC__
137static RTXBD rtx __attribute__ ((aligned(8)));
138#else
139#error "rtx must be 64-bit aligned"
140#endif
141
wdenk2a8af182005-04-13 10:02:42 +0000142#undef ET_DEBUG
wdenk42d1f032003-10-15 23:53:47 +0000143
144static int fec_send(struct eth_device* dev, volatile void *packet, int length)
145{
146 int i = 0;
147 int result = 0;
148
149 if (length <= 0) {
150 printf("fec: bad packet size: %d\n", length);
151 goto out;
152 }
153
154 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
155 if (i >= TOUT_LOOP) {
156 printf("fec: tx buffer not ready\n");
157 goto out;
158 }
159 }
160
161 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
162 rtx.txbd[txIdx].cbd_datlen = length;
163 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
wdenka6310922005-04-21 21:10:22 +0000164 BD_ENET_TX_TC | BD_ENET_TX_PAD);
wdenk42d1f032003-10-15 23:53:47 +0000165
166 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
167 if (i >= TOUT_LOOP) {
168 printf("fec: tx error\n");
169 goto out;
170 }
171 }
172
173#ifdef ET_DEBUG
174 printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
175 printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
176 for(i=0;i<(length/16 + 1);i++) {
177 printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
178 *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
179 *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
180 }
181#endif
182
183 /* return only status bits */
184 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
185 txIdx = (txIdx + 1) % TX_BUF_CNT;
186
187out:
188 return result;
189}
190
191static int fec_recv(struct eth_device* dev)
192{
193 int length;
194
195 for (;;)
196 {
197 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
198 length = -1;
199 break; /* nothing received - leave for() loop */
200 }
201 length = rtx.rxbd[rxIdx].cbd_datlen;
202
203 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
204 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
205 }
206 else {
207 /* Pass the packet up to the protocol layers. */
208 NetReceive(NetRxPackets[rxIdx], length - 4);
209 }
210
211
212 /* Give the buffer back to the FCC. */
213 rtx.rxbd[rxIdx].cbd_datlen = 0;
214
215 /* wrap around buffer index when necessary */
216 if ((rxIdx + 1) >= PKTBUFSRX) {
217 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
218 rxIdx = 0;
219 }
220 else {
221 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
222 rxIdx++;
223 }
224 }
225 return length;
226}
227
228
229static int fec_init(struct eth_device* dev, bd_t *bis)
230{
231 struct ether_fcc_info_s * info = dev->priv;
232 int i;
Kumar Galaaafeefb2007-11-28 00:36:33 -0600233 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
234 volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
wdenk42d1f032003-10-15 23:53:47 +0000235 fcc_enet_t *pram_ptr;
236 unsigned long mem_addr;
237
238#if 0
239 mii_discover_phy();
240#endif
241
242 /* 28.9 - (1-2): ioports have been set up already */
243
244 /* 28.9 - (3): connect FCC's tx and rx clocks */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600245 cpm->im_cpm_mux.cmxuar = 0; /* ATM */
246 cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
wdenk42d1f032003-10-15 23:53:47 +0000247 info->cmxfcr_value;
248
249 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
250 if(info->ether_index == 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600251 cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
wdenk42d1f032003-10-15 23:53:47 +0000252 } else if (info->ether_index == 1) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600253 cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
wdenk42d1f032003-10-15 23:53:47 +0000254 } else if (info->ether_index == 2) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600255 cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
wdenk42d1f032003-10-15 23:53:47 +0000256 }
257
258 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
259 if(info->ether_index == 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600260 cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
wdenk42d1f032003-10-15 23:53:47 +0000261 } else if (info->ether_index == 1){
Kumar Galaaafeefb2007-11-28 00:36:33 -0600262 cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
wdenk42d1f032003-10-15 23:53:47 +0000263 } else if (info->ether_index == 2){
Kumar Galaaafeefb2007-11-28 00:36:33 -0600264 cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
wdenk42d1f032003-10-15 23:53:47 +0000265 }
266
267 /* 28.9 - (6): FDSR: Ethernet Syn */
268 if(info->ether_index == 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600269 cpm->im_cpm_fcc1.fdsr = 0xD555;
wdenk42d1f032003-10-15 23:53:47 +0000270 } else if (info->ether_index == 1) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600271 cpm->im_cpm_fcc2.fdsr = 0xD555;
wdenk42d1f032003-10-15 23:53:47 +0000272 } else if (info->ether_index == 2) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600273 cpm->im_cpm_fcc3.fdsr = 0xD555;
wdenk42d1f032003-10-15 23:53:47 +0000274 }
275
276 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
277 rxIdx = 0;
278 txIdx = 0;
279
280 /* Setup Receiver Buffer Descriptors */
281 for (i = 0; i < PKTBUFSRX; i++)
282 {
283 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
284 rtx.rxbd[i].cbd_datlen = 0;
285 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
286 }
287 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
288
289 /* Setup Ethernet Transmitter Buffer Descriptors */
290 for (i = 0; i < TX_BUF_CNT; i++)
291 {
292 rtx.txbd[i].cbd_sc = 0;
293 rtx.txbd[i].cbd_datlen = 0;
294 rtx.txbd[i].cbd_bufaddr = 0;
295 }
296 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
297
298 /* 28.9 - (7): initialize parameter ram */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600299 pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
wdenk42d1f032003-10-15 23:53:47 +0000300
301 /* clear whole structure to make sure all reserved fields are zero */
302 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
303
304 /*
305 * common Parameter RAM area
306 *
307 * Allocate space in the reserved FCC area of DPRAM for the
308 * internal buffers. No one uses this space (yet), so we
309 * can do this. Later, we will add resource management for
Wolfgang Denka889bd22005-12-06 15:02:31 +0100310 * this area.
311 * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560
312 * 0x9000 for MPC8541, MPC8555
wdenk42d1f032003-10-15 23:53:47 +0000313 */
314 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
315 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
316 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
317 /*
318 * Set maximum bytes per receive buffer.
319 * It must be a multiple of 32.
320 */
321 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
322 /* localbus SDRAM should be preferred */
323 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
324 CFG_CPMFCR_RAMTYPE) << 24;
325 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
326 pram_ptr->fen_genfcc.fcc_rbdstat = 0;
327 pram_ptr->fen_genfcc.fcc_rbdlen = 0;
328 pram_ptr->fen_genfcc.fcc_rdptr = 0;
329 /* localbus SDRAM should be preferred */
330 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
331 CFG_CPMFCR_RAMTYPE) << 24;
332 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
333 pram_ptr->fen_genfcc.fcc_tbdstat = 0;
334 pram_ptr->fen_genfcc.fcc_tbdlen = 0;
335 pram_ptr->fen_genfcc.fcc_tdptr = 0;
336
337 /* protocol-specific area */
338 pram_ptr->fen_statbuf = 0x0;
339 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
340 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
341 pram_ptr->fen_crcec = 0;
342 pram_ptr->fen_alec = 0;
343 pram_ptr->fen_disfc = 0;
344 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
345 pram_ptr->fen_retcnt = 0;
346 pram_ptr->fen_pper = 0;
347 pram_ptr->fen_boffcnt = 0;
348 pram_ptr->fen_gaddrh = 0;
349 pram_ptr->fen_gaddrl = 0;
350 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
351 /*
352 * Set Ethernet station address.
353 *
354 * This is supplied in the board information structure, so we
355 * copy that into the controller.
356 * So far we have only been given one Ethernet address. We make
357 * it unique by setting a few bits in the upper byte of the
358 * non-static part of the address.
359 */
360#define ea eth_get_dev()->enetaddr
361 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
362 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
363 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
364#undef ea
365 pram_ptr->fen_ibdcount = 0;
366 pram_ptr->fen_ibdstart = 0;
367 pram_ptr->fen_ibdend = 0;
368 pram_ptr->fen_txlen = 0;
369 pram_ptr->fen_iaddrh = 0; /* disable hash */
370 pram_ptr->fen_iaddrl = 0;
371 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
372 /* pad pointer. use tiptr since we don't need a specific padding char */
373 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
374 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
375 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
376
377#if defined(ET_DEBUG)
378 printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
379 printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
380 pram_ptr->fen_genfcc.fcc_rbase);
381 printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
382 pram_ptr->fen_genfcc.fcc_tbase);
383#endif
384
385 /* 28.9 - (8)(9): clear out events in FCCE */
386 /* 28.9 - (9): FCCM: mask all events */
387 if(info->ether_index == 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600388 cpm->im_cpm_fcc1.fcce = ~0x0;
389 cpm->im_cpm_fcc1.fccm = 0;
wdenk42d1f032003-10-15 23:53:47 +0000390 } else if (info->ether_index == 1) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600391 cpm->im_cpm_fcc2.fcce = ~0x0;
392 cpm->im_cpm_fcc2.fccm = 0;
wdenk42d1f032003-10-15 23:53:47 +0000393 } else if (info->ether_index == 2) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600394 cpm->im_cpm_fcc3.fcce = ~0x0;
395 cpm->im_cpm_fcc3.fccm = 0;
wdenk42d1f032003-10-15 23:53:47 +0000396 }
397
398 /* 28.9 - (10-12): we don't use ethernet interrupts */
399
400 /* 28.9 - (13)
401 *
402 * Let's re-initialize the channel now. We have to do it later
403 * than the manual describes because we have just now finished
404 * the BD initialization.
405 */
406 cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
407 info->cpm_cr_enet_sblock,
408 0x0c,
409 CPM_CR_INIT_TRX) | CPM_CR_FLG;
410 do {
411 __asm__ __volatile__ ("eieio");
412 } while (cp->cpcr & CPM_CR_FLG);
413
414 /* 28.9 - (14): enable tx/rx in gfmr */
415 if(info->ether_index == 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600416 cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
wdenk42d1f032003-10-15 23:53:47 +0000417 } else if (info->ether_index == 1) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600418 cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
wdenk42d1f032003-10-15 23:53:47 +0000419 } else if (info->ether_index == 2) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600420 cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
wdenk42d1f032003-10-15 23:53:47 +0000421 }
422
wdenka6310922005-04-21 21:10:22 +0000423 return 1;
wdenk42d1f032003-10-15 23:53:47 +0000424}
425
426static void fec_halt(struct eth_device* dev)
427{
428 struct ether_fcc_info_s * info = dev->priv;
Kumar Galaaafeefb2007-11-28 00:36:33 -0600429 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000430
431 /* write GFMR: disable tx/rx */
432 if(info->ether_index == 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600433 cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
wdenk42d1f032003-10-15 23:53:47 +0000434 } else if(info->ether_index == 1) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600435 cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
wdenk42d1f032003-10-15 23:53:47 +0000436 } else if(info->ether_index == 2) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600437 cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
wdenk42d1f032003-10-15 23:53:47 +0000438 }
439}
440
441int fec_initialize(bd_t *bis)
442{
443 struct eth_device* dev;
444 int i;
445
446 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
447 {
448 dev = (struct eth_device*) malloc(sizeof *dev);
449 memset(dev, 0, sizeof *dev);
450
451 sprintf(dev->name, "FCC%d ETHERNET",
452 ether_fcc_info[i].ether_index + 1);
453 dev->priv = &ether_fcc_info[i];
454 dev->init = fec_init;
455 dev->halt = fec_halt;
456 dev->send = fec_send;
457 dev->recv = fec_recv;
458
459 eth_register(dev);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200460
Jon Loeliger44312832007-07-09 19:06:00 -0500461#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200462 && defined(CONFIG_BITBANGMII)
463 miiphy_register(dev->name,
464 bb_miiphy_read, bb_miiphy_write);
465#endif
wdenk42d1f032003-10-15 23:53:47 +0000466 }
467
468 return 1;
469}
470
Jon Loeliger068b60a2007-07-10 10:27:39 -0500471#endif
wdenk42d1f032003-10-15 23:53:47 +0000472
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500473#endif /* CONFIG_CPM2 */