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Michal Simek4ed97322020-01-09 10:28:56 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP ZCU1285 RevA
4 *
Michal Simekd31f1c92020-02-18 08:38:06 +01005 * (C) Copyright 2018 - 2020, Xilinx, Inc.
Michal Simek4ed97322020-01-09 10:28:56 +01006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15
16/ {
17 model = "ZynqMP ZCU1285 RevA";
18 compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
19 "xlnx,zynqmp";
20
21 aliases {
22 serial0 = &uart0;
23 serial1 = &dcc;
24 spi0 = &qspi;
25 mmc0 = &sdhci1;
Harini Katakam0e3a7aa2020-02-18 14:20:18 +053026 ethernet0 = &gem1; /* EMIO */
Michal Simek4ed97322020-01-09 10:28:56 +010027 i2c = &i2c0; /* EMIO */
28 };
29
30 chosen {
31 bootargs = "earlycon";
32 stdout-path = "serial0:115200n8";
33 };
34
35 memory@0 {
36 device_type = "memory";
37 reg = <0x0 0x0 0x0 0x80000000>;
38 };
39
40 ina226-u60 {
41 compatible = "iio-hwmon";
42 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
43 };
44 ina226-u61 {
45 compatible = "iio-hwmon";
46 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
47 };
48 ina226-u63 {
49 compatible = "iio-hwmon";
50 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
51 };
52 ina226-u65 {
53 compatible = "iio-hwmon";
54 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
55 };
56 ina226-u64 {
57 compatible = "iio-hwmon";
58 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
59 };
60};
61
62&dcc {
63 status = "okay";
64};
65
66&i2c0 {
67 status = "okay";
68 clock-frequency = <400000>;
69
70 i2c-mux@75 {
71 compatible = "nxp,pca9548"; /* u22 */
72 #address-cells = <1>;
73 #size-cells = <0>;
74 reg = <0x75>;
75
76 i2c@0 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 reg = <0>;
80 /* PMBUS */
81 max20751@74 { /* u23 */
82 compatible = "maxim,max20751";
83 reg = <0x74>;
84 };
85 max20751@70 { /* u89 */
86 compatible = "maxim,max20751";
87 reg = <0x70>;
88 };
89 max15301@a { /* u28 */
90 compatible = "maxim,max15301";
91 reg = <0xa>;
92 };
93 max15303@b { /* u48 */
94 compatible = "maxim,max15303";
95 reg = <0xb>;
96 };
97 max15303@d { /* u27 */
98 compatible = "maxim,max15303";
99 reg = <0xd>;
100 };
101 max15303@e { /* u11 */
102 compatible = "maxim,max15303";
103 reg = <0xe>;
104 };
105 max15303@f { /* u96 */
106 compatible = "maxim,max15303";
107 reg = <0xf>;
108 };
109 max15303@11 { /* u47 */
110 compatible = "maxim,max15303";
111 reg = <0x11>;
112 };
113 max15303@12 { /* u24 */
114 compatible = "maxim,max15303";
115 reg = <0x12>;
116 };
117 max15301@13 { /* u29 */
118 compatible = "maxim,max15301";
119 reg = <0x13>;
120 };
121 max15303@14 { /* u51 */
122 compatible = "maxim,max15303";
123 reg = <0x14>;
124 };
125 max15303@15 { /* u30 */
126 compatible = "maxim,max15303";
127 reg = <0x15>;
128 };
129 max15303@16 { /* u102 */
130 compatible = "maxim,max15303";
131 reg = <0x16>;
132 };
133 max15301@17 { /* u50 */
134 compatible = "maxim,max15301";
135 reg = <0x17>;
136 };
137 max15301@18 { /* u31 */
138 compatible = "maxim,max15301";
139 reg = <0x18>;
140 };
141 };
142 i2c@1 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 reg = <1>;
146 /* CM_I2C */
147 };
148 i2c@2 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 reg = <2>;
152 /* SYS_EEPROM */
153 eeprom: eeprom@54 { /* u101 */
154 compatible = "atmel,24c32"; /* 24LC32A */
155 reg = <0x54>;
156 };
157 };
158 i2c@3 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 reg = <3>;
162 /* FMC1 */
163 };
164 i2c@4 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <4>;
168 /* FMC2 */
169 };
170 i2c@5 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 reg = <5>;
174 /* ANALOG_PMBUS */
175 u60: ina226@40 { /* u60 */
176 compatible = "ti,ina226";
177 #io-channel-cells = <1>;
178 label = "ina226-u60";
179 reg = <0x40>;
180 shunt-resistor = <1000>;
181 };
182 u61: ina226@41 { /* u61 */
183 compatible = "ti,ina226";
184 #io-channel-cells = <1>;
185 label = "ina226-u61";
186 reg = <0x41>;
187 shunt-resistor = <1000>;
188 };
189 u63: ina226@42 { /* u63 */
190 compatible = "ti,ina226";
191 #io-channel-cells = <1>;
192 label = "ina226-u63";
193 reg = <0x42>;
194 shunt-resistor = <1000>;
195 };
196 u65: ina226@43 { /* u65 */
197 compatible = "ti,ina226";
198 #io-channel-cells = <1>;
199 label = "ina226-u65";
200 reg = <0x43>;
201 shunt-resistor = <1000>;
202 };
203 u64: ina226@44 { /* u64 */
204 compatible = "ti,ina226";
205 #io-channel-cells = <1>;
206 label = "ina226-u64";
207 reg = <0x44>;
208 shunt-resistor = <1000>;
209 };
210 };
211 i2c@6 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 reg = <6>;
215 /* ANALOG_CM_I2C */
216 };
217 i2c@7 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 reg = <7>;
221 /* FMC3 */
222 };
223 };
224};
225
Harini Katakam0e3a7aa2020-02-18 14:20:18 +0530226&gem1 {
227 mdio {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 phy1: ethernet-phy@1 {
231 reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
232 rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
233 txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
234 txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
235 rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
236 rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
237 rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
238 rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
239 rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
240 txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
241 txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
242 txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
243 txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
244 };
245 };
246};
247
Michal Simek351b9f52021-05-11 13:59:01 +0200248&gpio {
249 status = "okay";
250};
251
Michal Simek4ed97322020-01-09 10:28:56 +0100252&qspi {
253 status = "okay";
254 flash@0 {
255 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
256 #address-cells = <1>;
257 #size-cells = <1>;
258 reg = <0x0>;
259 spi-tx-bus-width = <1>;
260 spi-rx-bus-width = <1>;
261 spi-max-frequency = <108000000>; /* Based on DC1 spec */
262 };
263};
264
265&uart0 {
266 status = "okay";
267};
268
269&sdhci1 {
270 status = "okay";
Manish Narani12ffe752020-02-13 23:37:30 -0700271 /*
272 * This property should be removed for supporting UHS mode
273 */
274 no-1-8-v;
Michal Simek01a6da12020-07-22 17:42:43 +0200275 xlnx,mio-bank = <1>;
Michal Simek4ed97322020-01-09 10:28:56 +0100276};