| Yuantian Tang | 353f36d | 2019-04-10 16:43:34 +0800 | [diff] [blame^] | 1 | Overview |
| 2 | -------- |
| 3 | The LS1028A Reference Design (RDB) is a high-performance computing, |
| 4 | evaluation, and development platform that supports ARM SoC LS1028A and its |
| 5 | derivatives. |
| 6 | |
| 7 | LS1028A SoC Overview |
| 8 | -------------------------------------- |
| 9 | Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc |
| 10 | |
| 11 | RDB Default Switch Settings (1: ON; 0: OFF) |
| 12 | ------------------------------------------- |
| 13 | For XSPI NOR boot (default) |
| 14 | SW2: 1111_1000 |
| 15 | SW3: 1111_0000 |
| 16 | SW5: 0011_1001 |
| 17 | |
| 18 | For SD Boot |
| 19 | SW2: 1000_1000 |
| 20 | SW3: 1111_0000 |
| 21 | SW5: 0011_1001 |
| 22 | |
| 23 | For eMMC Boot |
| 24 | SW2: 1001_1000 |
| 25 | SW3: 1111_0000 |
| 26 | SW5: 0011_1001 |
| 27 | |
| 28 | LS1028ARDB board Overview |
| 29 | ------------------------- |
| 30 | Processor |
| 31 | Two Arm Cortex- A72 processor cores: |
| 32 | - Based on 64-bit ARMv8 architecture |
| 33 | - Up to 1.3 GHz operation |
| 34 | - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 |
| 35 | data cache |
| 36 | - Arranged as a single cluster of two cores sharing a single 1 MB L2 |
| 37 | cache |
| 38 | DDR memory |
| 39 | - Five onboard 1G x8 discrete memory modules (Four data byte lanes |
| 40 | ECC) |
| 41 | - 32-bit data and 4-bit ECC |
| 42 | - One chip select |
| 43 | - Data transfer rates of up to 1.6 GT/s |
| 44 | - Single-bit error correction and double-bit error detection ECC (4-bit |
| 45 | check word across 32-bit data) |
| 46 | High-speed serial ports(SerDes) |
| 47 | - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the |
| 48 | Qualcomm AR8033 PHY |
| 49 | - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected |
| 50 | through the NXP F104S8A PHY |
| 51 | - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3 |
| 52 | (8 Gbit/s) cards |
| 53 | - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B |
| 54 | slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or |
| 55 | SATA Gen 3 cards (6 Gbit/s) at a time |
| 56 | eSDHC |
| 57 | - eSDHC1, eSDHC2 |
| 58 | SPI |
| 59 | - Connects to two mikroBUS sockets to support mikro-click modules, |
| 60 | such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near |
| 61 | field communications (NFC) controller |
| 62 | Octal SPI (XSPI) |
| 63 | - One 256 MB onboard XSPI serial NOR flash memory |
| 64 | - One 512 MB onboard XSPI serial NAND flash memory |
| 65 | - Supports a QSPI emulator for offboard QSPI emulation |
| 66 | I2C |
| 67 | - All system devices are accessed via I2C1, which is multiplexed on |
| 68 | I2C multiplexer PCA9848 to isolate address conflicts and reduce |
| 69 | capacitive load |
| 70 | - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor, |
| 71 | thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules |
| 72 | 1 and 2 |
| 73 | CAN |
| 74 | - The two CAN DB9 ports can support CAN FD fast phase at data rates of |
| 75 | up to 5 Mbit/s |
| 76 | Serial audio interface(SAI) |
| 77 | - Audio codec SGTL5000 provides headphone and audio LINEOUT for |
| 78 | stereo speakers |
| 79 | - IEEE1588 interface to support audio on SAI4 |