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Magnus Lilja40c642b2009-06-13 20:50:01 +02001/*
Magnus Lilja40c642b2009-06-13 20:50:01 +02002 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __FSL_NFC_H
24#define __FSL_NFC_H
25
26/*
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020027 * Register map and bit definitions for the Freescale NAND Flash Controller
28 * present in various i.MX devices.
John Rigbyf3bb63a2010-01-26 19:24:17 -070029 *
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020030 * MX31 and MX27 have version 1, which has:
31 * 4 512-byte main buffers and
32 * 4 16-byte spare buffers
33 * to support up to 2K byte pagesize nand.
34 * Reading or writing a 2K page requires 4 FDI/FDO cycles.
John Rigbyf3bb63a2010-01-26 19:24:17 -070035 *
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +020036 * MX25 and MX35 have version 2.1, which has:
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020037 * 8 512-byte main buffers and
38 * 8 64-byte spare buffers
39 * to support up to 4K byte pagesize nand.
40 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
41 * Also some of registers are moved and/or changed meaning as seen below.
Magnus Lilja40c642b2009-06-13 20:50:01 +020042 */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020043#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
John Rigbyf3bb63a2010-01-26 19:24:17 -070044#define MXC_NFC_V1
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +020045#define is_mxc_nfc_1() 1
46#define is_mxc_nfc_21() 0
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020047#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +020048#define MXC_NFC_V2_1
49#define is_mxc_nfc_1() 0
50#define is_mxc_nfc_21() 1
John Rigbyf3bb63a2010-01-26 19:24:17 -070051#else
Benoît Thébaudeau1884d652012-08-13 22:50:42 +020052#error "MXC NFC implementation not supported"
John Rigbyf3bb63a2010-01-26 19:24:17 -070053#endif
54
55#if defined(MXC_NFC_V1)
56#define NAND_MXC_NR_BUFS 4
57#define NAND_MXC_SPARE_BUF_SIZE 16
58#define NAND_MXC_REG_OFFSET 0xe00
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020059#define NAND_MXC_2K_MULTI_CYCLE
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +020060#elif defined(MXC_NFC_V2_1)
John Rigbyf3bb63a2010-01-26 19:24:17 -070061#define NAND_MXC_NR_BUFS 8
62#define NAND_MXC_SPARE_BUF_SIZE 64
63#define NAND_MXC_REG_OFFSET 0x1e00
John Rigbyf3bb63a2010-01-26 19:24:17 -070064#endif
Magnus Lilja40c642b2009-06-13 20:50:01 +020065
66struct fsl_nfc_regs {
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020067 u8 main_area[NAND_MXC_NR_BUFS][0x200];
68 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
John Rigbyf3bb63a2010-01-26 19:24:17 -070069 /*
70 * reserved size is offset of nfc registers
71 * minus total main and spare sizes
72 */
73 u8 reserved1[NAND_MXC_REG_OFFSET
74 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
75#if defined(MXC_NFC_V1)
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020076 u16 buf_size;
Magnus Lilja40c642b2009-06-13 20:50:01 +020077 u16 reserved2;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020078 u16 buf_addr;
79 u16 flash_addr;
Magnus Lilja40c642b2009-06-13 20:50:01 +020080 u16 flash_cmd;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020081 u16 config;
Magnus Lilja40c642b2009-06-13 20:50:01 +020082 u16 ecc_status_result;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020083 u16 rsltmain_area;
84 u16 rsltspare_area;
85 u16 wrprot;
86 u16 unlockstart_blkaddr;
87 u16 unlockend_blkaddr;
88 u16 nf_wrprst;
89 u16 config1;
90 u16 config2;
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +020091#elif defined(MXC_NFC_V2_1)
John Rigbyf3bb63a2010-01-26 19:24:17 -070092 u16 reserved2[2];
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020093 u16 buf_addr;
94 u16 flash_addr;
John Rigbyf3bb63a2010-01-26 19:24:17 -070095 u16 flash_cmd;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020096 u16 config;
Benoît Thébaudeauc1db8dd2012-08-13 22:49:42 +020097 u32 ecc_status_result;
John Rigbyf3bb63a2010-01-26 19:24:17 -070098 u16 spare_area_size;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020099 u16 wrprot;
John Rigbyf3bb63a2010-01-26 19:24:17 -0700100 u16 reserved3[2];
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200101 u16 nf_wrprst;
102 u16 config1;
103 u16 config2;
John Rigbyf3bb63a2010-01-26 19:24:17 -0700104 u16 reserved4;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200105 u16 unlockstart_blkaddr;
106 u16 unlockend_blkaddr;
107 u16 unlockstart_blkaddr1;
108 u16 unlockend_blkaddr1;
109 u16 unlockstart_blkaddr2;
110 u16 unlockend_blkaddr2;
111 u16 unlockstart_blkaddr3;
112 u16 unlockend_blkaddr3;
John Rigbyf3bb63a2010-01-26 19:24:17 -0700113#endif
Magnus Lilja40c642b2009-06-13 20:50:01 +0200114};
115
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000116/* Set FCMD to 1, rest to 0 for Command operation */
117#define NFC_CMD 0x1
Magnus Lilja40c642b2009-06-13 20:50:01 +0200118
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000119/* Set FADD to 1, rest to 0 for Address operation */
120#define NFC_ADDR 0x2
Magnus Lilja40c642b2009-06-13 20:50:01 +0200121
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000122/* Set FDI to 1, rest to 0 for Input operation */
123#define NFC_INPUT 0x4
Magnus Lilja40c642b2009-06-13 20:50:01 +0200124
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000125/* Set FDO to 001, rest to 0 for Data Output operation */
126#define NFC_OUTPUT 0x8
Magnus Lilja40c642b2009-06-13 20:50:01 +0200127
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000128/* Set FDO to 010, rest to 0 for Read ID operation */
129#define NFC_ID 0x10
Magnus Lilja40c642b2009-06-13 20:50:01 +0200130
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000131/* Set FDO to 100, rest to 0 for Read Status operation */
132#define NFC_STATUS 0x20
Magnus Lilja40c642b2009-06-13 20:50:01 +0200133
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000134#define NFC_CONFIG1_SP_EN (1 << 2)
135#define NFC_CONFIG1_RST (1 << 6)
136#define NFC_CONFIG1_CE (1 << 7)
137#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
138#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
139#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
140#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
141#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
142#define NFC_V2_CONFIG1_FP_INT (1 << 11)
Magnus Lilja40c642b2009-06-13 20:50:01 +0200143
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000144#define NFC_V1_V2_CONFIG2_INT (1 << 15)
145
146#define operation config2
147#define readnfc readw
148#define writenfc writew
Magnus Lilja40c642b2009-06-13 20:50:01 +0200149
150#endif /* __FSL_NFC_H */