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Etienne Carriere358599e2020-09-09 18:44:00 +02001/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
4 * Copyright (C) 2019-2020, Linaro Limited
5 */
6#ifndef _SCMI_PROTOCOLS_H
7#define _SCMI_PROTOCOLS_H
8
9#include <linux/bitops.h>
Etienne Carriere60388842020-09-09 18:44:04 +020010#include <asm/types.h>
Etienne Carriere358599e2020-09-09 18:44:00 +020011
12/*
13 * Subset the SCMI protocols definition
14 * based on SCMI specification v2.0 (DEN0056B)
15 * https://developer.arm.com/docs/den0056/b
16 */
17
18enum scmi_std_protocol {
19 SCMI_PROTOCOL_ID_BASE = 0x10,
20 SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
21 SCMI_PROTOCOL_ID_SYSTEM = 0x12,
22 SCMI_PROTOCOL_ID_PERF = 0x13,
23 SCMI_PROTOCOL_ID_CLOCK = 0x14,
24 SCMI_PROTOCOL_ID_SENSOR = 0x15,
25 SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
26};
27
28enum scmi_status_code {
29 SCMI_SUCCESS = 0,
30 SCMI_NOT_SUPPORTED = -1,
31 SCMI_INVALID_PARAMETERS = -2,
32 SCMI_DENIED = -3,
33 SCMI_NOT_FOUND = -4,
34 SCMI_OUT_OF_RANGE = -5,
35 SCMI_BUSY = -6,
36 SCMI_COMMS_ERROR = -7,
37 SCMI_GENERIC_ERROR = -8,
38 SCMI_HARDWARE_ERROR = -9,
39 SCMI_PROTOCOL_ERROR = -10,
40};
41
Etienne Carriere60388842020-09-09 18:44:04 +020042/*
43 * SCMI Clock Protocol
44 */
45
46enum scmi_clock_message_id {
47 SCMI_CLOCK_RATE_SET = 0x5,
48 SCMI_CLOCK_RATE_GET = 0x6,
49 SCMI_CLOCK_CONFIG_SET = 0x7,
50};
51
52#define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0)
53#define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1))
54#define SCMI_CLK_RATE_ROUND_DOWN 0
55#define SCMI_CLK_RATE_ROUND_UP BIT(2)
56#define SCMI_CLK_RATE_ROUND_CLOSEST BIT(3)
57
58/**
59 * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command
60 * @clock_id: SCMI clock ID
61 * @attributes: Attributes of the targets clock state
62 */
63struct scmi_clk_state_in {
64 u32 clock_id;
65 u32 attributes;
66};
67
68/**
69 * struct scmi_clk_state_out - Response payload for CLOCK_CONFIG_SET command
70 * @status: SCMI command status
71 */
72struct scmi_clk_state_out {
73 s32 status;
74};
75
76/**
77 * struct scmi_clk_state_in - Message payload for CLOCK_RATE_GET command
78 * @clock_id: SCMI clock ID
79 * @attributes: Attributes of the targets clock state
80 */
81struct scmi_clk_rate_get_in {
82 u32 clock_id;
83};
84
85/**
86 * struct scmi_clk_rate_get_out - Response payload for CLOCK_RATE_GET command
87 * @status: SCMI command status
88 * @rate_lsb: 32bit LSB of the clock rate in Hertz
89 * @rate_msb: 32bit MSB of the clock rate in Hertz
90 */
91struct scmi_clk_rate_get_out {
92 s32 status;
93 u32 rate_lsb;
94 u32 rate_msb;
95};
96
97/**
98 * struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command
99 * @clock_id: SCMI clock ID
100 * @flags: Flags for the clock rate set request
101 * @rate_lsb: 32bit LSB of the clock rate in Hertz
102 * @rate_msb: 32bit MSB of the clock rate in Hertz
103 */
104struct scmi_clk_rate_set_in {
105 u32 clock_id;
106 u32 flags;
107 u32 rate_lsb;
108 u32 rate_msb;
109};
110
111/**
112 * struct scmi_clk_rate_set_out - Response payload for CLOCK_RATE_SET command
113 * @status: SCMI command status
114 */
115struct scmi_clk_rate_set_out {
116 s32 status;
117};
118
Etienne Carriere34d76fe2020-09-09 18:44:06 +0200119/*
120 * SCMI Reset Domain Protocol
121 */
122
123enum scmi_reset_domain_message_id {
124 SCMI_RESET_DOMAIN_ATTRIBUTES = 0x3,
125 SCMI_RESET_DOMAIN_RESET = 0x4,
126};
127
128#define SCMI_RD_NAME_LEN 16
129
130#define SCMI_RD_ATTRIBUTES_FLAG_ASYNC BIT(31)
131#define SCMI_RD_ATTRIBUTES_FLAG_NOTIF BIT(30)
132
133#define SCMI_RD_RESET_FLAG_ASYNC BIT(2)
134#define SCMI_RD_RESET_FLAG_ASSERT BIT(1)
135#define SCMI_RD_RESET_FLAG_CYCLE BIT(0)
136
137/**
138 * struct scmi_rd_attr_in - Payload for RESET_DOMAIN_ATTRIBUTES message
139 * @domain_id: SCMI reset domain ID
140 */
141struct scmi_rd_attr_in {
142 u32 domain_id;
143};
144
145/**
146 * struct scmi_rd_attr_out - Payload for RESET_DOMAIN_ATTRIBUTES response
147 * @status: SCMI command status
148 * @attributes: Retrieved attributes of the reset domain
149 * @latency: Reset cycle max lantency
150 * @name: Reset domain name
151 */
152struct scmi_rd_attr_out {
153 s32 status;
154 u32 attributes;
155 u32 latency;
156 char name[SCMI_RD_NAME_LEN];
157};
158
159/**
160 * struct scmi_rd_reset_in - Message payload for RESET command
161 * @domain_id: SCMI reset domain ID
162 * @flags: Flags for the reset request
163 * @reset_state: Reset target state
164 */
165struct scmi_rd_reset_in {
166 u32 domain_id;
167 u32 flags;
168 u32 reset_state;
169};
170
171/**
172 * struct scmi_rd_reset_out - Response payload for RESET command
173 * @status: SCMI command status
174 */
175struct scmi_rd_reset_out {
176 s32 status;
177};
178
Etienne Carriere358599e2020-09-09 18:44:00 +0200179#endif /* _SCMI_PROTOCOLS_H */