blob: 03688a51a301149b2e4e731dc821ccd6d8ac749e [file] [log] [blame]
Dave Gerlachb6059dd2021-04-23 11:27:46 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
11};
12
13&cbass_main{
14 u-boot,dm-spl;
15 timer1: timer@2400000 {
16 compatible = "ti,omap5430-timer";
17 reg = <0x0 0x2400000 0x0 0x80>;
18 ti,timer-alwon;
19 clock-frequency = <250000000>;
20 u-boot,dm-spl;
21 };
22};
23
Lokesh Vutla93e0bfb2021-05-06 16:44:56 +053024&main_conf {
25 u-boot,dm-spl;
26 chipid@14 {
27 u-boot,dm-spl;
28 };
29};
30
Lokesh Vutla45b7a9f2021-05-06 16:44:58 +053031&main_pmx0 {
32 u-boot,dm-spl;
33 main_i2c0_pins_default: main-i2c0-pins-default {
34 u-boot,dm-spl;
35 pinctrl-single,pins = <
36 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
37 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
38 >;
39 };
40};
41
42&main_i2c0 {
43 u-boot,dm-spl;
44 pinctrl-names = "default";
45 pinctrl-0 = <&main_i2c0_pins_default>;
46 clock-frequency = <400000>;
47};
48
Dave Gerlachb6059dd2021-04-23 11:27:46 -050049&main_uart0 {
50 u-boot,dm-spl;
51};
52
Aswath Govindraju1c8b4042021-06-04 22:00:37 +053053&usb0 {
54 dr_mode="peripheral";
55 u-boot,dm-spl;
56};
57
58&usbss0 {
59 u-boot,dm-spl;
60};
61
Aswath Govindraju7ca1af62021-08-09 22:32:23 +053062&main_mmc1_pins_default {
63 u-boot,dm-spl;
64};
65
Aswath Govindraju1c8b4042021-06-04 22:00:37 +053066&main_usb0_pins_default {
67 u-boot,dm-spl;
68};
69
Dave Gerlachb6059dd2021-04-23 11:27:46 -050070&dmss {
71 u-boot,dm-spl;
72};
73
74&secure_proxy_main {
75 u-boot,dm-spl;
76};
77
78&dmsc {
79 u-boot,dm-spl;
Suman Annaa97ee922021-05-13 20:10:56 -050080 k3_sysreset: sysreset-controller {
81 compatible = "ti,sci-sysreset";
82 u-boot,dm-spl;
83 };
Dave Gerlachb6059dd2021-04-23 11:27:46 -050084};
85
86&k3_pds {
87 u-boot,dm-spl;
88};
89
90&k3_clks {
91 u-boot,dm-spl;
92};
93
94&k3_reset {
95 u-boot,dm-spl;
96};
97
98&sdhci0 {
99 u-boot,dm-spl;
100};
101
102&sdhci1 {
103 u-boot,dm-spl;
104};
Vignesh Raghavendrabc17fcc2021-05-10 20:06:12 +0530105
106&cpsw3g {
107 reg = <0x0 0x8000000 0x0 0x200000>,
108 <0x0 0x43000200 0x0 0x8>;
109 reg-names = "cpsw_nuss", "mac_efuse";
110 /delete-property/ ranges;
111
112 cpsw-phy-sel@04044 {
113 compatible = "ti,am64-phy-gmii-sel";
114 reg = <0x0 0x43004044 0x0 0x8>;
115 };
116};
117
118&cpsw_port2 {
119 status = "disabled";
120};