blob: 9d751f6b2f225464013fff84202818e40fd773e6 [file] [log] [blame]
Ley Foon Tan35b98002017-04-26 02:44:43 +08001/*
2 * Copyright (C) 2016-2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <altera.h>
8#include <common.h>
9#include <errno.h>
10#include <fdtdec.h>
11#include <miiphy.h>
12#include <netdev.h>
13#include <ns16550.h>
14#include <watchdog.h>
15#include <asm/arch/misc.h>
16#include <asm/arch/pinmux.h>
17#include <asm/arch/reset_manager.h>
18#include <asm/arch/sdram_arria10.h>
19#include <asm/arch/system_manager.h>
20#include <asm/arch/nic301.h>
21#include <asm/io.h>
22#include <asm/pl310.h>
23
24#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
25#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
26#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
27#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
28#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
29#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#if defined(CONFIG_SPL_BUILD)
34static struct pl310_regs *const pl310 =
35 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
36static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
37 (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
38#endif
39
40static struct socfpga_system_manager *sysmgr_regs =
41 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
42
43/*
44 * DesignWare Ethernet initialization
45 */
46#ifdef CONFIG_ETH_DESIGNWARE
47void dwmac_deassert_reset(const unsigned int of_reset_id,
48 const u32 phymode)
49{
50 u32 reset;
51
52 if (of_reset_id == EMAC0_RESET) {
53 reset = SOCFPGA_RESET(EMAC0);
54 } else if (of_reset_id == EMAC1_RESET) {
55 reset = SOCFPGA_RESET(EMAC1);
56 } else if (of_reset_id == EMAC2_RESET) {
57 reset = SOCFPGA_RESET(EMAC2);
58 } else {
59 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
60 return;
61 }
62
63 clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
64 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
65 phymode);
66
67 /* Release the EMAC controller from reset */
68 socfpga_per_reset(reset, 0);
69}
70#endif
71
72#if defined(CONFIG_SPL_BUILD)
73/*
74+ * This function initializes security policies to be consistent across
75+ * all logic units in the Arria 10.
76+ *
77+ * The idea is to set all security policies to be normal, nonsecure
78+ * for all units.
79+ */
80static void initialize_security_policies(void)
81{
82 /* Put OCRAM in non-secure */
83 writel(0x003f0000, &noc_fw_ocram_base->region0);
84 writel(0x1, &noc_fw_ocram_base->enable);
85}
86
87int arch_early_init_r(void)
88{
89 initialize_security_policies();
90
91 /* Configure the L2 controller to make SDRAM start at 0 */
92 writel(0x1, &pl310->pl310_addr_filter_start);
93
94 /* assert reset to all except L4WD0 and L4TIMER0 */
95 socfpga_per_reset_all();
96
97 /* configuring the clock based on handoff */
98 /* TODO: Add call to cm_basic_init() */
99
100 /* Add device descriptor to FPGA device table */
101 socfpga_fpga_add();
102 return 0;
103}
104#else
105int arch_early_init_r(void)
106{
107 return 0;
108}
109#endif
110
111/*
112 * This function looking the 1st encounter UART peripheral,
113 * and then return its offset of the dedicated/shared IO pin
114 * mux. offset value (zero and above).
115 */
116static int find_peripheral_uart(const void *blob,
117 int child, const char *node_name)
118{
119 int len;
120 fdt_addr_t base_addr = 0;
121 fdt_size_t size;
122 const u32 *cell;
123 u32 value, offset = 0;
124
125 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
126 if (base_addr != FDT_ADDR_T_NONE) {
127 cell = fdt_getprop(blob, child, "pinctrl-single,pins",
128 &len);
129 if (cell != NULL) {
130 for (; len > 0; len -= (2 * sizeof(u32))) {
131 offset = fdt32_to_cpu(*cell++);
132 value = fdt32_to_cpu(*cell++);
133 /* Found UART peripheral. */
134 if (value == PINMUX_UART)
135 return offset;
136 }
137 }
138 }
139 return -EINVAL;
140}
141
142/*
143 * This function looks up the 1st encounter UART peripheral,
144 * and then return its offset of the dedicated/shared IO pin
145 * mux. UART peripheral is found if the offset is not in negative
146 * value.
147 */
148static int is_peripheral_uart_true(const void *blob,
149 int node, const char *child_name)
150{
151 int child, len;
152 const char *node_name;
153
154 child = fdt_first_subnode(blob, node);
155
156 if (child < 0)
157 return -EINVAL;
158
159 node_name = fdt_get_name(blob, child, &len);
160
161 while (node_name) {
162 if (!strcmp(child_name, node_name))
163 return find_peripheral_uart(blob, child, node_name);
164
165 child = fdt_next_subnode(blob, child);
166 if (child < 0)
167 break;
168
169 node_name = fdt_get_name(blob, child, &len);
170 }
171
172 return -1;
173}
174
175/*
176 * This function looking the 1st encounter UART dedicated IO peripheral,
177 * and then return based address of the 1st encounter UART dedicated
178 * IO peripheral.
179 */
180unsigned int dedicated_uart_com_port(const void *blob)
181{
182 int node;
183
184 node = fdtdec_next_compatible(blob, 0,
185 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
186 if (node < 0)
187 return 0;
188
189 if (is_peripheral_uart_true(blob, node, "dedicated") >= 0)
190 return SOCFPGA_UART1_ADDRESS;
191
192 return 0;
193}
194
195/*
196 * This function looking the 1st encounter UART shared IO peripheral, and then
197 * return based address of the 1st encounter UART shared IO peripheral.
198 */
199unsigned int shared_uart_com_port(const void *blob)
200{
201 int node, ret;
202
203 node = fdtdec_next_compatible(blob, 0,
204 COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
205 if (node < 0)
206 return 0;
207
208 ret = is_peripheral_uart_true(blob, node, "shared");
209
210 if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 ||
211 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 ||
212 ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3)
213 return SOCFPGA_UART0_ADDRESS;
214 else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 ||
215 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 ||
216 ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3)
217 return SOCFPGA_UART1_ADDRESS;
218
219 return 0;
220}
221
222/*
223 * This function looking the 1st encounter UART peripheral, and then return
224 * base address of the 1st encounter UART peripheral.
225 */
226unsigned int uart_com_port(const void *blob)
227{
228 unsigned int ret;
229
230 ret = dedicated_uart_com_port(blob);
231
232 if (ret)
233 return ret;
234
235 return shared_uart_com_port(blob);
236}
237
238/*
239 * Print CPU information
240 */
241#if defined(CONFIG_DISPLAY_CPUINFO)
242int print_cpuinfo(void)
243{
244 const u32 bsel =
245 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
246
247 puts("CPU: Altera SoCFPGA Arria 10\n");
248
249 printf("BOOT: %s\n", bsel_str[bsel].name);
250 return 0;
251}
252#endif
253
254#ifdef CONFIG_ARCH_MISC_INIT
255int arch_misc_init(void)
256{
257 return 0;
258}
259#endif