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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4e5ca3e2003-12-08 01:34:36 +00002/*
wdenkbf9e3b32004-02-12 00:47:09 +00003 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 *
5 * (C) Copyright 2000
wdenk4e5ca3e2003-12-08 01:34:36 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk4e5ca3e2003-12-08 01:34:36 +00007 */
8
9#include <common.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
Simon Glassc30b7ad2019-11-14 12:57:41 -070011#include <irq_func.h>
Simon Glass6887c5b2019-11-14 12:57:26 -070012#include <time.h>
Simon Glass401d1c42020-10-30 21:38:53 -060013#include <asm/global_data.h>
Simon Glassc05ed002020-05-10 11:40:11 -060014#include <linux/delay.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000015
TsiChungLiew52b01762007-07-05 23:36:16 -050016#include <asm/timer.h>
17#include <asm/immap.h>
Richard Retanubun42a83762009-03-20 15:30:10 -040018#include <watchdog.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000019
TsiChungLiew99c03c12007-08-05 03:58:52 -050020DECLARE_GLOBAL_DATA_PTR;
21
Richard Retanubun42a83762009-03-20 15:30:10 -040022static volatile ulong timestamp = 0;
23
Tom Rini6e7df1d2023-01-10 11:19:45 -050024#ifndef CFG_SYS_WATCHDOG_FREQ
25#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
Richard Retanubun42a83762009-03-20 15:30:10 -040026#endif
stroesecd42dee2004-12-16 17:56:09 +000027
Marek Vasut35d48ea2023-03-23 01:20:39 +010028#if CONFIG_IS_ENABLED(MCFTMR)
Tom Rini6e7df1d2023-01-10 11:19:45 -050029#ifndef CFG_SYS_UDELAY_BASE
TsiChung Liew8e585f02007-06-18 13:50:13 -050030# error "uDelay base not defined!"
31#endif
32
Tom Rini6e7df1d2023-01-10 11:19:45 -050033#if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK)
TsiChung Liew8e585f02007-06-18 13:50:13 -050034# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
35#endif
TsiChungLiew52b01762007-07-05 23:36:16 -050036extern void dtimer_intr_setup(void);
TsiChung Liew8e585f02007-06-18 13:50:13 -050037
Ingo van Lil3eb90ba2009-11-24 14:09:21 +010038void __udelay(unsigned long usec)
TsiChung Liew8e585f02007-06-18 13:50:13 -050039{
Tom Rini6e7df1d2023-01-10 11:19:45 -050040 volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050041 uint start, now, tmp;
42
43 while (usec > 0) {
44 if (usec > 65000)
45 tmp = 65000;
46 else
47 tmp = usec;
48 usec = usec - tmp;
49
50 /* Set up TIMER 3 as timebase clock */
51 timerp->tmr = DTIM_DTMR_RST_RST;
52 timerp->tcn = 0;
53 /* set period to 1 us */
54 timerp->tmr =
Tom Rini6e7df1d2023-01-10 11:19:45 -050055 CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
TsiChungLiew52b01762007-07-05 23:36:16 -050056 DTIM_DTMR_RST_EN;
TsiChung Liew8e585f02007-06-18 13:50:13 -050057
58 start = now = timerp->tcn;
59 while (now < start + tmp)
60 now = timerp->tcn;
61 }
62}
63
64void dtimer_interrupt(void *not_used)
65{
Tom Rini6e7df1d2023-01-10 11:19:45 -050066 volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050067
68 /* check for timer interrupt asserted */
Tom Rini6e7df1d2023-01-10 11:19:45 -050069 if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) {
TsiChung Liew8e585f02007-06-18 13:50:13 -050070 timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
71 timestamp++;
Richard Retanubun42a83762009-03-20 15:30:10 -040072
73 #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
Tom Rini6e7df1d2023-01-10 11:19:45 -050074 if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) {
Stefan Roese29caf932022-09-02 14:10:46 +020075 schedule();
Richard Retanubun42a83762009-03-20 15:30:10 -040076 }
77 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
TsiChung Liew8e585f02007-06-18 13:50:13 -050078 return;
79 }
80}
81
Jason Jin444ddfc2011-08-19 10:02:32 +080082int timer_init(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050083{
Tom Rini6e7df1d2023-01-10 11:19:45 -050084 volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050085
86 timestamp = 0;
87
88 timerp->tcn = 0;
89 timerp->trr = 0;
90
91 /* Set up TIMER 4 as clock */
92 timerp->tmr = DTIM_DTMR_RST_RST;
93
TsiChungLiew52b01762007-07-05 23:36:16 -050094 /* initialize and enable timer interrupt */
Tom Rini6e7df1d2023-01-10 11:19:45 -050095 irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
TsiChung Liew8e585f02007-06-18 13:50:13 -050096
97 timerp->tcn = 0;
98 timerp->trr = 1000; /* Interrupt every ms */
99
TsiChungLiew52b01762007-07-05 23:36:16 -0500100 dtimer_intr_setup();
TsiChung Liew8e585f02007-06-18 13:50:13 -0500101
102 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
Tom Rini6e7df1d2023-01-10 11:19:45 -0500103 timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
TsiChung Liew8e585f02007-06-18 13:50:13 -0500104 DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
Jason Jin444ddfc2011-08-19 10:02:32 +0800105
106 return 0;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500107}
108
TsiChung Liew8e585f02007-06-18 13:50:13 -0500109ulong get_timer(ulong base)
110{
111 return (timestamp - base);
112}
113
Marek Vasut35d48ea2023-03-23 01:20:39 +0100114#endif /* CONFIG_MCFTMR */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500115
wdenk70f05ac2004-06-09 15:24:18 +0000116/*
117 * This function is derived from PowerPC code (read timebase as long long).
118 * On M68K it just returns the timer value.
119 */
120unsigned long long get_ticks(void)
121{
122 return get_timer(0);
123}
124
Stefan Roesef2302d42008-08-06 14:05:38 +0200125unsigned long usec2ticks(unsigned long usec)
126{
127 return get_timer(usec);
128}
129
wdenk70f05ac2004-06-09 15:24:18 +0000130/*
131 * This function is derived from PowerPC code (timebase clock frequency).
132 * On M68K it returns the number of timer ticks per second.
133 */
TsiChungLiew52b01762007-07-05 23:36:16 -0500134ulong get_tbclk(void)
wdenk70f05ac2004-06-09 15:24:18 +0000135{
Masahiro Yamada63a75782016-09-06 22:17:38 +0900136 return CONFIG_SYS_HZ;
wdenk70f05ac2004-06-09 15:24:18 +0000137}