blob: 1af9ba686d95d927d2fff266af9b13df731020df [file] [log] [blame]
York Sunb5b06fb2012-12-23 19:25:27 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunb5b06fb2012-12-23 19:25:27 +00005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
York Sun15672c62014-04-30 14:43:49 -070010#define CONFIG_SYS_GENERIC_BOARD
11#define CONFIG_DISPLAY_BOARDINFO
12
York Sunb5b06fb2012-12-23 19:25:27 +000013/*
14 * B4860 QDS board configuration file
15 */
16#define CONFIG_B4860QDS
17#define CONFIG_PHYS_64BIT
18
19#ifdef CONFIG_RAMBOOT_PBL
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053020#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
21#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
22#ifndef CONFIG_NAND
York Sunb5b06fb2012-12-23 19:25:27 +000023#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +053025#else
26#define CONFIG_SPL
27#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
28#define CONFIG_SPL_ENV_SUPPORT
29#define CONFIG_SPL_SERIAL_SUPPORT
30#define CONFIG_SPL_FLUSH_IMAGE
31#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
32#define CONFIG_SPL_LIBGENERIC_SUPPORT
33#define CONFIG_SPL_LIBCOMMON_SUPPORT
34#define CONFIG_SPL_I2C_SUPPORT
35#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
36#define CONFIG_FSL_LAW /* Use common FSL init code */
37#define CONFIG_SYS_TEXT_BASE 0x00201000
38#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
39#define CONFIG_SPL_PAD_TO 0x40000
40#define CONFIG_SPL_MAX_SIZE 0x28000
41#define RESET_VECTOR_OFFSET 0x27FFC
42#define BOOT_PAGE_OFFSET 0x27000
43#define CONFIG_SPL_NAND_SUPPORT
44#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
45#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
46#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
47#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
48#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
49#define CONFIG_SPL_NAND_BOOT
50#ifdef CONFIG_SPL_BUILD
51#define CONFIG_SPL_SKIP_RELOCATE
52#define CONFIG_SPL_COMMON_INIT_DDR
53#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
54#define CONFIG_SYS_NO_FLASH
55#endif
56#endif
York Sunb5b06fb2012-12-23 19:25:27 +000057#endif
58
Liu Gang5870fe42013-05-07 16:30:48 +080059#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
60/* Set 1M boot space */
61#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
62#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
63 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
64#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
65#define CONFIG_SYS_NO_FLASH
66#endif
67
York Sunb5b06fb2012-12-23 19:25:27 +000068/* High Level Configuration Options */
69#define CONFIG_BOOKE
York Sunb5b06fb2012-12-23 19:25:27 +000070#define CONFIG_E500 /* BOOKE e500 family */
71#define CONFIG_E500MC /* BOOKE e500mc family */
72#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
York Sunb5b06fb2012-12-23 19:25:27 +000073#define CONFIG_MP /* support multiple processors */
74
75#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053076#define CONFIG_SYS_TEXT_BASE 0xeff40000
York Sunb5b06fb2012-12-23 19:25:27 +000077#endif
78
79#ifndef CONFIG_RESET_VECTOR_ADDRESS
80#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
81#endif
82
83#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
84#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
85#define CONFIG_FSL_IFC /* Enable IFC Support */
86#define CONFIG_PCI /* Enable PCI/PCIE */
87#define CONFIG_PCIE1 /* PCIE controler 1 */
88#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
89#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
90
91#ifndef CONFIG_PPC_B4420
92#define CONFIG_SYS_SRIO
93#define CONFIG_SRIO1 /* SRIO port 1 */
94#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang3a017992013-05-07 16:30:47 +080095#define CONFIG_SRIO_PCIE_BOOT_MASTER
York Sunb5b06fb2012-12-23 19:25:27 +000096#endif
97
98#define CONFIG_FSL_LAW /* Use common FSL init code */
99
100/* I2C bus multiplexer */
101#define I2C_MUX_PCA_ADDR 0x77
102
103/* VSC Crossbar switches */
104#define CONFIG_VSC_CROSSBAR
105#define I2C_CH_DEFAULT 0x8
106#define I2C_CH_VSC3316 0xc
107#define I2C_CH_VSC3308 0xd
108
109#define VSC3316_TX_ADDRESS 0x70
110#define VSC3316_RX_ADDRESS 0x71
111#define VSC3308_TX_ADDRESS 0x02
112#define VSC3308_RX_ADDRESS 0x03
113
Shaveta Leekhacb033742013-07-02 14:43:53 +0530114/* IDT clock synthesizers */
115#define CONFIG_IDT8T49N222A
116#define I2C_CH_IDT 0x9
117
118#define IDT_SERDES1_ADDRESS 0x6E
119#define IDT_SERDES2_ADDRESS 0x6C
120
Shaveta Leekha652e29b2014-04-11 14:12:40 +0530121/* Voltage monitor on channel 2*/
122#define I2C_MUX_CH_VOL_MONITOR 0xa
123#define I2C_VOL_MONITOR_ADDR 0x40
124#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
125#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
126#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
127
128#define CONFIG_ZM7300
129#define I2C_MUX_CH_DPM 0xa
130#define I2C_DPM_ADDR 0x28
131
York Sunb5b06fb2012-12-23 19:25:27 +0000132#define CONFIG_ENV_OVERWRITE
133
134#ifdef CONFIG_SYS_NO_FLASH
Liu Gang5870fe42013-05-07 16:30:48 +0800135#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
York Sunb5b06fb2012-12-23 19:25:27 +0000136#define CONFIG_ENV_IS_NOWHERE
Liu Gang5870fe42013-05-07 16:30:48 +0800137#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000138#else
139#define CONFIG_FLASH_CFI_DRIVER
140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
142#endif
143
York Sunb5b06fb2012-12-23 19:25:27 +0000144#if defined(CONFIG_SPIFLASH)
145#define CONFIG_SYS_EXTRA_ENV_RELOC
146#define CONFIG_ENV_IS_IN_SPI_FLASH
147#define CONFIG_ENV_SPI_BUS 0
148#define CONFIG_ENV_SPI_CS 0
149#define CONFIG_ENV_SPI_MAX_HZ 10000000
150#define CONFIG_ENV_SPI_MODE 0
151#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
152#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
153#define CONFIG_ENV_SECT_SIZE 0x10000
154#elif defined(CONFIG_SDCARD)
155#define CONFIG_SYS_EXTRA_ENV_RELOC
156#define CONFIG_ENV_IS_IN_MMC
157#define CONFIG_SYS_MMC_ENV_DEV 0
158#define CONFIG_ENV_SIZE 0x2000
159#define CONFIG_ENV_OFFSET (512 * 1097)
160#elif defined(CONFIG_NAND)
161#define CONFIG_SYS_EXTRA_ENV_RELOC
162#define CONFIG_ENV_IS_IN_NAND
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530163#define CONFIG_ENV_SIZE 0x2000
164#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800165#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
166#define CONFIG_ENV_IS_IN_REMOTE
167#define CONFIG_ENV_ADDR 0xffe20000
168#define CONFIG_ENV_SIZE 0x2000
169#elif defined(CONFIG_ENV_IS_NOWHERE)
170#define CONFIG_ENV_SIZE 0x2000
York Sunb5b06fb2012-12-23 19:25:27 +0000171#else
172#define CONFIG_ENV_IS_IN_FLASH
173#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
174#define CONFIG_ENV_SIZE 0x2000
175#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
176#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000177
178#ifndef __ASSEMBLY__
179unsigned long get_board_sys_clk(void);
180unsigned long get_board_ddr_clk(void);
181#endif
182#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
183#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
184
185/*
186 * These can be toggled for performance analysis, otherwise use default.
187 */
188#define CONFIG_SYS_CACHE_STASHING
189#define CONFIG_BTB /* toggle branch predition */
190#define CONFIG_DDR_ECC
191#ifdef CONFIG_DDR_ECC
192#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
193#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
194#endif
195
196#define CONFIG_ENABLE_36BIT_PHYS
197
198#ifdef CONFIG_PHYS_64BIT
199#define CONFIG_ADDR_MAP
200#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
201#endif
202
203#if 0
204#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
205#endif
206#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
207#define CONFIG_SYS_MEMTEST_END 0x00400000
208#define CONFIG_SYS_ALT_MEMTEST
209#define CONFIG_PANIC_HANG /* do not reset board on panic */
210
211/*
212 * Config the L3 Cache as L3 SRAM
213 */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530214#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
215#define CONFIG_SYS_L3_SIZE 256 << 10
216#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
217#ifdef CONFIG_NAND
218#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
219#endif
220#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
221#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
222#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
223#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
York Sunb5b06fb2012-12-23 19:25:27 +0000224
225#ifdef CONFIG_PHYS_64BIT
226#define CONFIG_SYS_DCSRBAR 0xf0000000
227#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
228#endif
229
230/* EEPROM */
231#define CONFIG_SYS_I2C_EEPROM_NXID
232#define CONFIG_SYS_EEPROM_BUS_NUM 0
233#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
234#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
235#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
237
238/*
239 * DDR Setup
240 */
241#define CONFIG_VERY_BIG_RAM
242#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
243#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
244
245/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
246#define CONFIG_DIMM_SLOTS_PER_CTLR 1
247#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
248
249#define CONFIG_DDR_SPD
250#define CONFIG_SYS_DDR_RAW_TIMING
York Sun5614e712013-09-30 09:22:09 -0700251#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530252#ifndef CONFIG_SPL_BUILD
York Sunb5b06fb2012-12-23 19:25:27 +0000253#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530254#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000255
256#define CONFIG_SYS_SPD_BUS_NUM 0
257#define SPD_EEPROM_ADDRESS1 0x51
258#define SPD_EEPROM_ADDRESS2 0x53
259
260#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
261#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
262
263/*
264 * IFC Definitions
265 */
266#define CONFIG_SYS_FLASH_BASE 0xe0000000
267#ifdef CONFIG_PHYS_64BIT
268#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
269#else
270#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
271#endif
272
273#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
274#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
275 + 0x8000000) | \
276 CSPR_PORT_SIZE_16 | \
277 CSPR_MSEL_NOR | \
278 CSPR_V)
279#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
280#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
281 CSPR_PORT_SIZE_16 | \
282 CSPR_MSEL_NOR | \
283 CSPR_V)
284#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
285/* NOR Flash Timing Params */
286#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
287#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
Prabhakar Kushwaha4d0e6e02013-05-17 13:40:52 +0530288 FTIM0_NOR_TEADC(0x04) | \
York Sunb5b06fb2012-12-23 19:25:27 +0000289 FTIM0_NOR_TEAHC(0x20))
290#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
291 FTIM1_NOR_TRAD_NOR(0x1A) |\
292 FTIM1_NOR_TSEQRAD_NOR(0x13))
293#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
294 FTIM2_NOR_TCH(0x0E) | \
295 FTIM2_NOR_TWPH(0x0E) | \
296 FTIM2_NOR_TWP(0x1c))
297#define CONFIG_SYS_NOR_FTIM3 0x0
298
299#define CONFIG_SYS_FLASH_QUIET_TEST
300#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
301
302#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
303#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
304#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
305#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
306
307#define CONFIG_SYS_FLASH_EMPTY_INFO
308#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
309 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
310
311#define CONFIG_FSL_QIXIS /* use common QIXIS code */
312#define CONFIG_FSL_QIXIS_V2
313#define QIXIS_BASE 0xffdf0000
314#ifdef CONFIG_PHYS_64BIT
315#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
316#else
317#define QIXIS_BASE_PHYS QIXIS_BASE
318#endif
319#define QIXIS_LBMAP_SWITCH 0x01
320#define QIXIS_LBMAP_MASK 0x0f
321#define QIXIS_LBMAP_SHIFT 0
322#define QIXIS_LBMAP_DFLTBANK 0x00
323#define QIXIS_LBMAP_ALTBANK 0x02
324#define QIXIS_RST_CTL_RESET 0x31
325#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
326#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
327#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
328
329#define CONFIG_SYS_CSPR3_EXT (0xf)
330#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
331 | CSPR_PORT_SIZE_8 \
332 | CSPR_MSEL_GPCM \
333 | CSPR_V)
334#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
335#define CONFIG_SYS_CSOR3 0x0
336/* QIXIS Timing parameters for IFC CS3 */
337#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
338 FTIM0_GPCM_TEADC(0x0e) | \
339 FTIM0_GPCM_TEAHC(0x0e))
340#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
341 FTIM1_GPCM_TRAD(0x1f))
342#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
343 FTIM2_GPCM_TCH(0x0) | \
344 FTIM2_GPCM_TWP(0x1f))
345#define CONFIG_SYS_CS3_FTIM3 0x0
346
347/* NAND Flash on IFC */
348#define CONFIG_NAND_FSL_IFC
York Sunab13ad52013-12-17 11:21:09 -0800349#define CONFIG_SYS_NAND_MAX_ECCPOS 256
350#define CONFIG_SYS_NAND_MAX_OOBFREE 2
York Sunb5b06fb2012-12-23 19:25:27 +0000351#define CONFIG_SYS_NAND_BASE 0xff800000
352#ifdef CONFIG_PHYS_64BIT
353#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
354#else
355#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
356#endif
357
358#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
359#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
360 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
361 | CSPR_MSEL_NAND /* MSEL = NAND */ \
362 | CSPR_V)
363#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
364
365#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
366 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
367 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
368 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
369 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
370 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
371 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
372
373#define CONFIG_SYS_NAND_ONFI_DETECTION
374
375/* ONFI NAND Flash mode0 Timing Params */
376#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
377 FTIM0_NAND_TWP(0x18) | \
378 FTIM0_NAND_TWCHT(0x07) | \
379 FTIM0_NAND_TWH(0x0a))
380#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
381 FTIM1_NAND_TWBE(0x39) | \
382 FTIM1_NAND_TRR(0x0e) | \
383 FTIM1_NAND_TRP(0x18))
384#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
385 FTIM2_NAND_TREH(0x0a) | \
386 FTIM2_NAND_TWHRE(0x1e))
387#define CONFIG_SYS_NAND_FTIM3 0x0
388
389#define CONFIG_SYS_NAND_DDR_LAW 11
390
391#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
392#define CONFIG_SYS_MAX_NAND_DEVICE 1
393#define CONFIG_MTD_NAND_VERIFY_WRITE
394#define CONFIG_CMD_NAND
395
396#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
397
398#if defined(CONFIG_NAND)
399#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
400#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
401#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
402#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
403#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
404#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
405#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
406#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
407#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
408#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
409#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
410#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
411#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
412#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
413#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
414#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
415#else
416#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
417#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
418#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
419#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
420#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
421#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
422#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
423#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
424#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
425#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
426#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
427#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
428#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
429#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
430#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
431#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
432#endif
433#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
434#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
435#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
436#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
437#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
438#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
439#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
440#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
441
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530442#ifdef CONFIG_SPL_BUILD
443#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
444#else
445#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
446#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000447
448#if defined(CONFIG_RAMBOOT_PBL)
449#define CONFIG_SYS_RAMBOOT
450#endif
451
452#define CONFIG_BOARD_EARLY_INIT_R
453#define CONFIG_MISC_INIT_R
454
455#define CONFIG_HWCONFIG
456
457/* define to use L1 as initial stack */
458#define CONFIG_L1_INIT_RAM
459#define CONFIG_SYS_INIT_RAM_LOCK
460#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
461#ifdef CONFIG_PHYS_64BIT
462#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
463#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
464/* The assembler doesn't like typecast */
465#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
466 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
467 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
468#else
469#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
470#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
471#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
472#endif
473#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
474
475#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
476 GENERATED_GBL_DATA_SIZE)
477#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
478
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530479#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
York Sunb5b06fb2012-12-23 19:25:27 +0000480#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
481
482/* Serial Port - controlled on board with jumper J8
483 * open - index 2
484 * shorted - index 1
485 */
486#define CONFIG_CONS_INDEX 1
487#define CONFIG_SYS_NS16550
488#define CONFIG_SYS_NS16550_SERIAL
489#define CONFIG_SYS_NS16550_REG_SIZE 1
490#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
491
492#define CONFIG_SYS_BAUDRATE_TABLE \
493 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
494
495#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
496#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
497#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
498#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
499#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530500#ifndef CONFIG_SPL_BUILD
York Sunb5b06fb2012-12-23 19:25:27 +0000501#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530502#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000503
504
505/* Use the HUSH parser */
506#define CONFIG_SYS_HUSH_PARSER
507#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
508
509/* pass open firmware flat tree */
510#define CONFIG_OF_LIBFDT
511#define CONFIG_OF_BOARD_SETUP
512#define CONFIG_OF_STDOUT_VIA_ALIAS
513
514/* new uImage format support */
515#define CONFIG_FIT
516#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
517
518/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200519#define CONFIG_SYS_I2C
520#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
521#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
522#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
523#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
524#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
525#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
526#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
York Sunb5b06fb2012-12-23 19:25:27 +0000527
528/*
529 * RTC configuration
530 */
531#define RTC
532#define CONFIG_RTC_DS3231 1
533#define CONFIG_SYS_I2C_RTC_ADDR 0x68
534
535/*
536 * RapidIO
537 */
538#ifdef CONFIG_SYS_SRIO
539#ifdef CONFIG_SRIO1
540#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
541#ifdef CONFIG_PHYS_64BIT
542#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
543#else
544#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
545#endif
546#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
547#endif
548
549#ifdef CONFIG_SRIO2
550#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
551#ifdef CONFIG_PHYS_64BIT
552#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
553#else
554#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
555#endif
556#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
557#endif
558#endif
559
560/*
561 * for slave u-boot IMAGE instored in master memory space,
562 * PHYS must be aligned based on the SIZE
563 */
Liu Gange4911812014-05-15 14:30:34 +0800564#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
565#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
566#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
567#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
York Sunb5b06fb2012-12-23 19:25:27 +0000568/*
569 * for slave UCODE and ENV instored in master memory space,
570 * PHYS must be aligned based on the SIZE
571 */
Liu Gange4911812014-05-15 14:30:34 +0800572#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
York Sunb5b06fb2012-12-23 19:25:27 +0000573#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
574#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
575
576/* slave core release by master*/
577#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
578#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
579
580/*
581 * SRIO_PCIE_BOOT - SLAVE
582 */
583#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
584#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
585#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
586 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
587#endif
588
589/*
590 * eSPI - Enhanced SPI
591 */
592#define CONFIG_FSL_ESPI
593#define CONFIG_SPI_FLASH
594#define CONFIG_SPI_FLASH_SST
595#define CONFIG_CMD_SF
596#define CONFIG_SF_DEFAULT_SPEED 10000000
597#define CONFIG_SF_DEFAULT_MODE 0
598
599/*
Shaveta Leekha6eaeba22013-03-25 07:40:24 +0000600 * MAPLE
601 */
602#ifdef CONFIG_PHYS_64BIT
603#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
604#else
605#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
606#endif
607
608/*
York Sunb5b06fb2012-12-23 19:25:27 +0000609 * General PCI
610 * Memory space is mapped 1-1, but I/O space must start from 0.
611 */
612
613/* controller 1, direct to uli, tgtid 3, Base address 20000 */
614#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
615#ifdef CONFIG_PHYS_64BIT
616#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
617#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
618#else
619#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
620#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
621#endif
622#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
623#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
624#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
625#ifdef CONFIG_PHYS_64BIT
626#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
627#else
628#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
629#endif
630#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
631
632/* Qman/Bman */
633#ifndef CONFIG_NOBQFMAN
634#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
635#define CONFIG_SYS_BMAN_NUM_PORTALS 25
636#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
637#ifdef CONFIG_PHYS_64BIT
638#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
639#else
640#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
641#endif
642#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
643#define CONFIG_SYS_QMAN_NUM_PORTALS 25
644#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
645#ifdef CONFIG_PHYS_64BIT
646#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
647#else
648#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
649#endif
650#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
651
652#define CONFIG_SYS_DPAA_FMAN
653
Minghuan Lian0795eff2013-07-03 18:32:41 +0800654#define CONFIG_SYS_DPAA_RMAN
655
York Sunb5b06fb2012-12-23 19:25:27 +0000656/* Default address of microcode for the Linux Fman driver */
657#if defined(CONFIG_SPIFLASH)
658/*
659 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
660 * env, so we got 0x110000.
661 */
662#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800663#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
York Sunb5b06fb2012-12-23 19:25:27 +0000664#elif defined(CONFIG_SDCARD)
665/*
666 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
667 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
668 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
669 */
670#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800671#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
York Sunb5b06fb2012-12-23 19:25:27 +0000672#elif defined(CONFIG_NAND)
673#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwahac5dfe6e2014-04-08 19:13:44 +0530674#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang5870fe42013-05-07 16:30:48 +0800675#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
676/*
677 * Slave has no ucode locally, it can fetch this from remote. When implementing
678 * in two corenet boards, slave's ucode could be stored in master's memory
679 * space, the address can be mapped from slave TLB->slave LAW->
680 * slave SRIO or PCIE outbound window->master inbound window->
681 * master LAW->the ucode address in master's memory space.
682 */
683#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800684#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
York Sunb5b06fb2012-12-23 19:25:27 +0000685#else
686#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800687#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
York Sunb5b06fb2012-12-23 19:25:27 +0000688#endif
689#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
690#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
691#endif /* CONFIG_NOBQFMAN */
692
693#ifdef CONFIG_SYS_DPAA_FMAN
694#define CONFIG_FMAN_ENET
695#define CONFIG_PHYLIB_10G
696#define CONFIG_PHY_VITESSE
697#define CONFIG_PHY_TERANETICS
698#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
699#define SGMII_CARD_PORT2_PHY_ADDR 0x10
700#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
701#define SGMII_CARD_PORT4_PHY_ADDR 0x11
702#endif
703
704#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000705#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunb5b06fb2012-12-23 19:25:27 +0000706#define CONFIG_NET_MULTI
707#define CONFIG_PCI_PNP /* do pci plug-and-play */
708#define CONFIG_E1000
709
710#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
711#define CONFIG_DOS_PARTITION
712#endif /* CONFIG_PCI */
713
714#ifdef CONFIG_FMAN_ENET
715#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
716#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
Suresh Gupta16d88f42013-03-25 07:40:13 +0000717
718/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
719#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
720#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
721
York Sunb5b06fb2012-12-23 19:25:27 +0000722
723#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
724#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
725#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
726#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
727
728#define CONFIG_MII /* MII PHY management */
729#define CONFIG_ETHPRIME "FM1@DTSEC1"
730#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
731#endif
732
733/*
734 * Environment
735 */
736#define CONFIG_LOADS_ECHO /* echo on for serial download */
737#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
738
739/*
740 * Command line configuration.
741 */
742#include <config_cmd_default.h>
743
744#define CONFIG_CMD_DATE
745#define CONFIG_CMD_DHCP
746#define CONFIG_CMD_EEPROM
747#define CONFIG_CMD_ELF
748#define CONFIG_CMD_ERRATA
749#define CONFIG_CMD_GREPENV
750#define CONFIG_CMD_IRQ
751#define CONFIG_CMD_I2C
752#define CONFIG_CMD_MII
753#define CONFIG_CMD_PING
754#define CONFIG_CMD_REGINFO
755#define CONFIG_CMD_SETEXPR
756
757#ifdef CONFIG_PCI
758#define CONFIG_CMD_PCI
759#define CONFIG_CMD_NET
760#endif
761
762/*
763* USB
764*/
765#define CONFIG_HAS_FSL_DR_USB
766
767#ifdef CONFIG_HAS_FSL_DR_USB
768#define CONFIG_USB_EHCI
769
770#ifdef CONFIG_USB_EHCI
771#define CONFIG_CMD_USB
772#define CONFIG_USB_STORAGE
773#define CONFIG_USB_EHCI_FSL
774#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
775#define CONFIG_CMD_EXT2
776#endif
777#endif
778
779/*
780 * Miscellaneous configurable options
781 */
782#define CONFIG_SYS_LONGHELP /* undef to save memory */
783#define CONFIG_CMDLINE_EDITING /* Command-line editing */
784#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
785#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
York Sunb5b06fb2012-12-23 19:25:27 +0000786#ifdef CONFIG_CMD_KGDB
787#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
788#else
789#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
790#endif
791#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
792#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
793#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
York Sunb5b06fb2012-12-23 19:25:27 +0000794
795/*
796 * For booting Linux, the board info and command line data
797 * have to be in the first 64 MB of memory, since this is
798 * the maximum mapped by the Linux kernel during initialization.
799 */
800#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
801#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
802
803#ifdef CONFIG_CMD_KGDB
804#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
York Sunb5b06fb2012-12-23 19:25:27 +0000805#endif
806
807/*
808 * Environment Configuration
809 */
810#define CONFIG_ROOTPATH "/opt/nfsroot"
811#define CONFIG_BOOTFILE "uImage"
812#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
813
814/* default location for tftp and bootm */
815#define CONFIG_LOADADDR 1000000
816
817#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
818
819#define CONFIG_BAUDRATE 115200
820
821#define __USB_PHY_TYPE ulpi
822
823#define CONFIG_EXTRA_ENV_SETTINGS \
824 "hwconfig=fsl_ddr:ctlr_intlv=null," \
825 "bank_intlv=cs0_cs1;" \
826 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
827 "netdev=eth0\0" \
828 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
829 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
830 "tftpflash=tftpboot $loadaddr $uboot && " \
831 "protect off $ubootaddr +$filesize && " \
832 "erase $ubootaddr +$filesize && " \
833 "cp.b $loadaddr $ubootaddr $filesize && " \
834 "protect on $ubootaddr +$filesize && " \
835 "cmp.b $loadaddr $ubootaddr $filesize\0" \
836 "consoledev=ttyS0\0" \
837 "ramdiskaddr=2000000\0" \
838 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
839 "fdtaddr=c00000\0" \
840 "fdtfile=b4860qds/b4860qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500841 "bdev=sda3\0"
York Sunb5b06fb2012-12-23 19:25:27 +0000842
843/* For emulation this causes u-boot to jump to the start of the proof point
844 app code automatically */
845#define CONFIG_PROOF_POINTS \
846 "setenv bootargs root=/dev/$bdev rw " \
847 "console=$consoledev,$baudrate $othbootargs;" \
848 "cpu 1 release 0x29000000 - - -;" \
849 "cpu 2 release 0x29000000 - - -;" \
850 "cpu 3 release 0x29000000 - - -;" \
851 "cpu 4 release 0x29000000 - - -;" \
852 "cpu 5 release 0x29000000 - - -;" \
853 "cpu 6 release 0x29000000 - - -;" \
854 "cpu 7 release 0x29000000 - - -;" \
855 "go 0x29000000"
856
857#define CONFIG_HVBOOT \
858 "setenv bootargs config-addr=0x60000000; " \
859 "bootm 0x01000000 - 0x00f00000"
860
861#define CONFIG_ALU \
862 "setenv bootargs root=/dev/$bdev rw " \
863 "console=$consoledev,$baudrate $othbootargs;" \
864 "cpu 1 release 0x01000000 - - -;" \
865 "cpu 2 release 0x01000000 - - -;" \
866 "cpu 3 release 0x01000000 - - -;" \
867 "cpu 4 release 0x01000000 - - -;" \
868 "cpu 5 release 0x01000000 - - -;" \
869 "cpu 6 release 0x01000000 - - -;" \
870 "cpu 7 release 0x01000000 - - -;" \
871 "go 0x01000000"
872
873#define CONFIG_LINUX \
874 "setenv bootargs root=/dev/ram rw " \
875 "console=$consoledev,$baudrate $othbootargs;" \
876 "setenv ramdiskaddr 0x02000000;" \
877 "setenv fdtaddr 0x00c00000;" \
878 "setenv loadaddr 0x1000000;" \
879 "bootm $loadaddr $ramdiskaddr $fdtaddr"
880
881#define CONFIG_HDBOOT \
882 "setenv bootargs root=/dev/$bdev rw " \
883 "console=$consoledev,$baudrate $othbootargs;" \
884 "tftp $loadaddr $bootfile;" \
885 "tftp $fdtaddr $fdtfile;" \
886 "bootm $loadaddr - $fdtaddr"
887
888#define CONFIG_NFSBOOTCOMMAND \
889 "setenv bootargs root=/dev/nfs rw " \
890 "nfsroot=$serverip:$rootpath " \
891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "tftp $loadaddr $bootfile;" \
894 "tftp $fdtaddr $fdtfile;" \
895 "bootm $loadaddr - $fdtaddr"
896
897#define CONFIG_RAMBOOTCOMMAND \
898 "setenv bootargs root=/dev/ram rw " \
899 "console=$consoledev,$baudrate $othbootargs;" \
900 "tftp $ramdiskaddr $ramdiskfile;" \
901 "tftp $loadaddr $bootfile;" \
902 "tftp $fdtaddr $fdtfile;" \
903 "bootm $loadaddr $ramdiskaddr $fdtaddr"
904
905#define CONFIG_BOOTCOMMAND CONFIG_LINUX
906
York Sunb5b06fb2012-12-23 19:25:27 +0000907#include <asm/fsl_secure_boot.h>
York Sunb5b06fb2012-12-23 19:25:27 +0000908
909#endif /* __CONFIG_H */