blob: a302f839a1ec239b9d96e83d4a5b26374a717f91 [file] [log] [blame]
Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - Configuration file for BF537 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF537_STAMP_H__
6#define __CONFIG_BF537_STAMP_H__
Aubrey Li26bf7de2007-03-19 01:24:52 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey Li26bf7de2007-03-19 01:24:52 +080010
11/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +080013 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysingercf6f4692008-06-01 09:09:48 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
Mike Frysingerf82caac2008-12-08 16:16:11 -050039#define CONFIG_SCLK_DIV 4
Mike Frysingercf6f4692008-06-01 09:09:48 -040040
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x306
49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
Sonic Zhang955020c2013-02-20 18:05:16 +080055#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Mike Frysingercf6f4692008-06-01 09:09:48 -040056#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
Aubrey Li26bf7de2007-03-19 01:24:52 +080058
59/*
60 * Network Settings
61 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040062#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
Aubrey Li26bf7de2007-03-19 01:24:52 +080065#define CONFIG_NETCONSOLE 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040066#endif
67#define CONFIG_HOSTNAME bf537-stamp
68/* Uncomment next line to use fixed MAC address */
69/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Masahiro Yamadac42f56d2014-04-18 19:09:49 +090070#define CONFIG_LIB_RAND
Jon Loeliger079a1362007-07-10 10:12:10 -050071
72/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040073 * Flash Settings
Jon Loeligerba2351f2007-07-04 22:31:49 -050074 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040075#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040077#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_FLASH_PROTECTION
79#define CONFIG_SYS_MAX_FLASH_BANKS 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040080/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
81#define CONFIG_SYS_MAX_FLASH_SECT 71
Aubrey Li26bf7de2007-03-19 01:24:52 +080082
Aubrey Li26bf7de2007-03-19 01:24:52 +080083
Mike Frysingercf6f4692008-06-01 09:09:48 -040084/*
85 * SPI Settings
86 */
87#define CONFIG_BFIN_SPI
88#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040089#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040090#define CONFIG_SPI_FLASH
Mike Frysingerf4532202010-09-19 16:26:55 -040091#define CONFIG_SPI_FLASH_ALL
Mike Frysingercf6f4692008-06-01 09:09:48 -040092
93
94/*
95 * Env Storage Settings
96 */
Mike Frysinger9171fc82008-03-30 15:46:13 -040097#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -040098#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +000099#define CONFIG_ENV_OFFSET 0x10000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200100#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000101#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400102#else
103#define CONFIG_ENV_IS_IN_FLASH
104#define CONFIG_ENV_OFFSET 0x4000
105#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
106#define CONFIG_ENV_SIZE 0x2000
107#define CONFIG_ENV_SECT_SIZE 0x2000
108#endif
109#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800110#define ENV_IS_EMBEDDED
Mike Frysingercf6f4692008-06-01 09:09:48 -0400111#else
Mike Frysinger76d82182009-07-21 22:17:36 -0400112#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercf6f4692008-06-01 09:09:48 -0400113#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400114#ifdef ENV_IS_EMBEDDED
115/* WARNING - the following is hand-optimized to fit within
116 * the sector before the environment sector. If it throws
117 * an error during compilation remove an object here to get
118 * it linked after the configuration sector.
119 */
120# define LDS_BOARD_TEXT \
Masahiro Yamadae2906a52013-11-11 14:36:00 +0900121 arch/blackfin/lib/built-in.o (.text*); \
122 arch/blackfin/cpu/built-in.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400123 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500124 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400125#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800126
Aubrey Li26bf7de2007-03-19 01:24:52 +0800127
128/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400129 * I2C Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800130 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400131#define CONFIG_BFIN_TWI_I2C 1
132#define CONFIG_HARD_I2C 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800133
Aubrey Li26bf7de2007-03-19 01:24:52 +0800134
135/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400136 * SPI_MMC Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800137 */
Sonic Zhang955020c2013-02-20 18:05:16 +0800138#define CONFIG_MMC_SPI
139#ifdef CONFIG_MMC_SPI
Mike Frysingercf6f4692008-06-01 09:09:48 -0400140#define CONFIG_MMC
Mike Frysinger14dda9d2010-12-24 12:53:47 -0500141#define CONFIG_GENERIC_MMC
Sonic Zhang955020c2013-02-20 18:05:16 +0800142#endif
Mike Frysingercf6f4692008-06-01 09:09:48 -0400143
144/*
145 * NAND Settings
146 */
Mike Frysingercd844232009-05-25 22:42:28 -0400147/* #define CONFIG_NAND_PLAT */
Sonic Zhang955020c2013-02-20 18:05:16 +0800148#ifdef CONFIG_NAND_PLAT
Mike Frysingercd844232009-05-25 22:42:28 -0400149#define CONFIG_SYS_NAND_BASE 0x20212000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MAX_NAND_DEVICE 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800151
Mike Frysingercd844232009-05-25 22:42:28 -0400152#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
153#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Mike Frysingercd844232009-05-25 22:42:28 -0400154#define BFIN_NAND_WRITE(addr, cmd) \
Mike Frysingercf6f4692008-06-01 09:09:48 -0400155 do { \
Mike Frysingercd844232009-05-25 22:42:28 -0400156 bfin_write8(addr, cmd); \
157 SSYNC(); \
Aubrey Li26bf7de2007-03-19 01:24:52 +0800158 } while (0)
159
Mike Frysingercd844232009-05-25 22:42:28 -0400160#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
161#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400162#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
Sonic Zhang955020c2013-02-20 18:05:16 +0800163#endif /* CONFIG_NAND_PLAT */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800164
165/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400166 * CF-CARD IDE-HDD Support
Aubrey Li26bf7de2007-03-19 01:24:52 +0800167 */
Michael Hennerichaa7b2482009-06-18 09:12:50 +0000168
169/*
170 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
171 * Strange address mapping Blackfin A13 connects to CF_A0
172 */
173
174/* #define CONFIG_BFIN_TRUE_IDE */
175
176/*
177 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
178 * This should be the preferred mode
179 */
180
181/* #define CONFIG_BFIN_CF_IDE */
182
183/*
184 * Add IDE Disk Drive (HDD) support
185 * See example interface here:
186 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
187 */
188
189/* #define CONFIG_BFIN_HDD_IDE */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800190
Mike Frysingercf6f4692008-06-01 09:09:48 -0400191#if defined(CONFIG_BFIN_CF_IDE) || \
192 defined(CONFIG_BFIN_HDD_IDE) || \
193 defined(CONFIG_BFIN_TRUE_IDE)
194# define CONFIG_BFIN_IDE 1
195# define CONFIG_CMD_IDE
196#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800197
Aubrey Li26bf7de2007-03-19 01:24:52 +0800198#if defined(CONFIG_BFIN_IDE)
199
200#define CONFIG_DOS_PARTITION 1
201/*
202 * IDE/ATA stuff
203 */
204#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
205#undef CONFIG_IDE_LED /* no led for ide supported */
206#undef CONFIG_IDE_RESET /* no reset for ide supported */
207
Mike Frysingercf6f4692008-06-01 09:09:48 -0400208#define CONFIG_SYS_IDE_MAXBUS 1
209#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800210
Mike Frysingercf6f4692008-06-01 09:09:48 -0400211#undef CONFIG_EBIU_AMBCTL1_VAL
212#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
Aubrey Li26bf7de2007-03-19 01:24:52 +0800213
214#define CONFIG_CF_ATASEL_DIS 0x20311800
215#define CONFIG_CF_ATASEL_ENA 0x20311802
216
217#if defined(CONFIG_BFIN_TRUE_IDE)
218/*
219 * Note that these settings aren't for the most part used in include/ata.h
220 * when all of the ATA registers are setup
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
223#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400224#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
225#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
226#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Michael Hennerichaa7b2482009-06-18 09:12:50 +0000227#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800228
Mike Frysingercf6f4692008-06-01 09:09:48 -0400229#elif defined(CONFIG_BFIN_CF_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
231#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400232#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
233#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
234#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
Michael Hennerichaa7b2482009-06-18 09:12:50 +0000235#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800236
Mike Frysingercf6f4692008-06-01 09:09:48 -0400237#elif defined(CONFIG_BFIN_HDD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
239#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400240#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
241#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
242#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800244#undef CONFIG_SCLK_DIV
245#define CONFIG_SCLK_DIV 8
Mike Frysingercf6f4692008-06-01 09:09:48 -0400246#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800247
Mike Frysingercf6f4692008-06-01 09:09:48 -0400248#endif
249
250
251/*
252 * Misc Settings
253 */
254#define CONFIG_MISC_INIT_R
255#define CONFIG_RTC_BFIN
256#define CONFIG_UART_CONSOLE 0
Masahiro Yamadae91df492014-03-05 16:59:37 +0900257#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
Mike Frysingercf6f4692008-06-01 09:09:48 -0400258
Mike Frysingercf6f4692008-06-01 09:09:48 -0400259/* Define if want to do post memory test */
260#undef CONFIG_POST
261#ifdef CONFIG_POST
Mike Frysinger0fc47442011-05-10 13:00:30 -0400262#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5
Mike Frysinger21513742011-05-10 16:22:25 -0400263#define CONFIG_POST_BSPEC1_GPIO_LEDS \
264 GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
265#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
266 GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
267#define CONFIG_POST_BSPEC2_GPIO_NAMES \
268 10, 11, 12, 13,
Mike Frysinger22f45ce2011-05-10 16:48:36 -0400269#define CONFIG_SYS_POST_FLASH_START 11
270#define CONFIG_SYS_POST_FLASH_END 71
Mike Frysingercf6f4692008-06-01 09:09:48 -0400271#endif
272
Mike Frysinger216818c2010-01-21 23:29:18 -0500273/* These are for board tests */
274#if 0
275#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
276#define CONFIG_AUTOBOOT_KEYED
277#define CONFIG_AUTOBOOT_PROMPT \
278 "autoboot in %d seconds: press space to stop\n", bootdelay
279#define CONFIG_AUTOBOOT_STOP_STR " "
280#endif
281
Mike Frysingercf6f4692008-06-01 09:09:48 -0400282
283/*
284 * Pull in common ADI header for remaining command/environment setup
285 */
286#include <configs/bfin_adi_common.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +0800287
Aubrey Li26bf7de2007-03-19 01:24:52 +0800288#endif