blob: b34e3422da73aafa33cff9ed8d9dfd894a92af86 [file] [log] [blame]
Matthias Weisser18a056a2010-08-09 13:31:51 +02001/*
2 * (C) Copyright 2010
3 * Matthias Weisser <weisserm@arcor.de>
4 *
5 * Configuation settings for the jadecpu board
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Matthias Weisser18a056a2010-08-09 13:31:51 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_MB86R0x
14#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
Matthias Weissera91916f2011-06-29 02:08:07 +000015#define CONFIG_SYS_TEXT_BASE 0x10000000
Matthias Weisser18a056a2010-08-09 13:31:51 +020016
17#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
Matthias Weisser18a056a2010-08-09 13:31:51 +020018
Matthias Weissera91916f2011-06-29 02:08:07 +000019#define CONFIG_USE_ARCH_MEMCPY
20#define CONFIG_USE_ARCH_MEMSET
21
Matthias Weisserb2a7bad2011-11-05 02:15:44 +000022#define MACH_TYPE_JADECPU 2636
23
24#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
25
Matthias Weisser18a056a2010-08-09 13:31:51 +020026/*
27 * Environment settings
28 */
29#define CONFIG_EXTRA_ENV_SETTINGS \
30 "gs_fast_boot=setenv bootdelay 5\0" \
31 "gs_slow_boot=setenv bootdelay 10\0" \
Matthias Weissera91916f2011-06-29 02:08:07 +000032 "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
Matthias Weisser18a056a2010-08-09 13:31:51 +020033 "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
34 "bootelf 0x40000000\0" \
35 ""
36
37#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38#define CONFIG_SETUP_MEMORY_TAGS 1
39#define CONFIG_INITRD_TAG 1
Helmut Raiger9660e442011-10-20 04:19:47 +000040#define CONFIG_BOARD_LATE_INIT
Matthias Weisser18a056a2010-08-09 13:31:51 +020041
42/*
43 * Compressions
44 */
45#define CONFIG_LZO
46
47/*
48 * Hardware drivers
49 */
50
51/*
52 * Serial
53 */
Matthias Weisser18a056a2010-08-09 13:31:51 +020054#define CONFIG_SYS_NS16550
55#define CONFIG_SYS_NS16550_SERIAL
56#define CONFIG_SYS_NS16550_REG_SIZE (-4)
57#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
58#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
59#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
60#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
61#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
62
63#define CONFIG_CONS_INDEX 4
64
65/*
66 * Ethernet
67 */
Matthias Weisser18a056a2010-08-09 13:31:51 +020068#define CONFIG_SMC911X
69#define CONFIG_SMC911X_BASE 0x02000000
70#define CONFIG_SMC911X_16_BIT
71
72/*
73 * Video
74 */
75#define CONFIG_VIDEO
76#define CONFIG_VIDEO_MB86R0xGDC
77#define CONFIG_SYS_WHITE_ON_BLACK
78#define CONFIG_CFB_CONSOLE
79#define CONFIG_SYS_CONSOLE_IS_IN_ENV
80#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
81#define CONFIG_VIDEO_LOGO
82#define CONFIG_SPLASH_SCREEN
83#define CONFIG_SPLASH_SCREEN_ALIGN
84#define CONFIG_VIDEO_BMP_LOGO
85#define CONFIG_VIDEO_BMP_GZIP
86#define CONFIG_VIDEO_BMP_RLE8
87#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
88#define VIDEO_FB_16BPP_WORD_SWAP
89#define VIDEO_KBD_INIT_FCT 0
90#define VIDEO_TSTC_FCT serial_tstc
91#define VIDEO_GETC_FCT serial_getc
92
93/*
94 * BOOTP options
95 */
96#define CONFIG_BOOTP_BOOTFILESIZE 1
97#define CONFIG_BOOTP_BOOTPATH 1
98#define CONFIG_BOOTP_GATEWAY 1
99#define CONFIG_BOOTP_HOSTNAME 1
100
101/*
102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105#undef CONFIG_CMD_BDI
106#undef CONFIG_CMD_FPGA
107#undef CONFIG_CMD_IMLS
108#undef CONFIG_CMD_LOADS
109#undef CONFIG_CMD_SOURCE
110#undef CONFIG_CMD_NFS
111#undef CONFIG_CMD_XIMG
112
Matthias Weissera91916f2011-06-29 02:08:07 +0000113#define CONFIG_CMD_BMP
Matthias Weissera91916f2011-06-29 02:08:07 +0000114#define CONFIG_CMD_DHCP
115#define CONFIG_CMD_ELF
116#define CONFIG_CMD_FAT
117#define CONFIG_CMD_PING
118#define CONFIG_CMD_USB
119#define CONFIG_CMD_CACHE
Matthias Weisser18a056a2010-08-09 13:31:51 +0200120
121#define CONFIG_SYS_HUSH_PARSER
Matthias Weisser18a056a2010-08-09 13:31:51 +0200122
123/* USB */
124#define CONFIG_USB_OHCI_NEW
125#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
126#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
127#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
128#define CONFIG_USB_STORAGE
129#define CONFIG_DOS_PARTITION
130
131/* SDRAM */
132#define CONFIG_NR_DRAM_BANKS 1
133#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
134#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
135
Matthias Weisserb9d74b42010-09-21 15:37:44 +0200136#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
137#define CONFIG_SYS_INIT_SP_ADDR 0x01008000
138
Matthias Weisser18a056a2010-08-09 13:31:51 +0200139/*
140 * FLASH and environment organization
141 */
142#define CONFIG_SYS_FLASH_BASE 0x10000000
143#define CONFIG_SYS_MAX_FLASH_BANKS 1
144#define CONFIG_SYS_MAX_FLASH_SECT 256
145#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
146
147#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
148#define CONFIG_ENV_IS_IN_FLASH 1
149#define CONFIG_ENV_SECT_SIZE (128 * 1024)
150#define CONFIG_ENV_SIZE (128 * 1024)
151
152/*
153 * CFI FLASH driver setup
154 */
155#define CONFIG_SYS_FLASH_CFI 1
156#define CONFIG_FLASH_CFI_DRIVER 1
157#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
158
159#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
160
161#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
162#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
163
164#define CONFIG_BAUDRATE 115200
Matthias Weisser18a056a2010-08-09 13:31:51 +0200165
166#define CONFIG_SYS_PROMPT "jade> "
167#define CONFIG_SYS_CBSIZE 256
168#define CONFIG_SYS_MAXARGS 16
169#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
170 sizeof(CONFIG_SYS_PROMPT) + 16)
171#define CONFIG_SYS_LONGHELP 1
172#define CONFIG_CMDLINE_EDITING 1
173
174#define CONFIG_PREBOOT ""
175
176#define CONFIG_BOOTDELAY 5
177#define CONFIG_AUTOBOOT_KEYED
178#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
179#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
180#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
181
182/*
183 * Size of malloc() pool
184 */
Matthias Weissera91916f2011-06-29 02:08:07 +0000185#define CONFIG_SYS_MALLOC_LEN (10 << 20)
186#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
Matthias Weisser18a056a2010-08-09 13:31:51 +0200187
Matthias Weisser18a056a2010-08-09 13:31:51 +0200188/*
189 * Clock reset generator init
190 */
191#define CONFIG_SYS_CRG_CRHA_INIT 0xffff
192#define CONFIG_SYS_CRG_CRPA_INIT 0xffff
193#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
194#define CONFIG_SYS_CRG_CRHB_INIT 0xffff
195#define CONFIG_SYS_CRG_CRAM_INIT 0xffef
196
197/*
198 * Memory controller settings
199 */
200#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
201#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
202#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
203#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
204#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
205#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
206#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
207#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
208#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
209
210/*
211 * DDR2 controller init settings
212 */
213#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
214#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
215#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
216#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
217#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
218#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
219#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
220#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
221#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
222#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
223#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
224#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
225#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
226#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
227#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
228#define CONFIG_SYS_DDR2_DROS_INIT 0x0001
229
230/*
231 * DRAM init sequence
232 */
233
234/* PALL Command */
235#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
236#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
237
238/* EMR(2) command */
239#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
240#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
241
242/* EMR(3) command */
243#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
244#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
245
246/* EMR(1) command */
247#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
248#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
249
250/* MRS command */
251#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
252#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
253
254/* PALL command */
255#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
256#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
257
258/* REF command 1 */
259#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
260#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
261
262/* MRS command */
263#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
264#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
265
266/* EMR(1) command */
267#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
268#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
269
270/* EMR(1) command */
271#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
272#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
273
Matthias Weisser18a056a2010-08-09 13:31:51 +0200274#endif /* __CONFIG_H */