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Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz991425f2006-03-14 16:24:38 +01006 */
7
8#include <common.h>
9#include <ioports.h>
10#include <mpc83xx.h>
11#include <asm/mpc8349_pci.h>
12#include <i2c.h>
Ben Warren80ddd222008-01-16 22:37:42 -050013#include <spi.h>
Marian Balakowicz991425f2006-03-14 16:24:38 +010014#include <miiphy.h>
York Sun5614e712013-09-30 09:22:09 -070015#ifdef CONFIG_SYS_FSL_DDR2
16#include <fsl_ddr_sdram.h>
York Sund4b91062011-08-26 11:32:45 -070017#else
Marian Balakowicz991425f2006-03-14 16:24:38 +010018#include <spd_sdram.h>
York Sund4b91062011-08-26 11:32:45 -070019#endif
Jon Loeligera30a5492008-03-04 10:03:03 -060020
Kim Phillipsb3458d22007-12-20 15:57:28 -060021#if defined(CONFIG_OF_LIBFDT)
Kim Phillips3fde9e82007-08-15 22:30:33 -050022#include <libfdt.h>
Kim Phillipsbf0b5422006-11-01 00:10:40 -060023#endif
24
Marian Balakowicz991425f2006-03-14 16:24:38 +010025int fixed_sdram(void);
26void sdram_init(void);
27
Peter Tyser0f898602009-05-22 17:23:24 -050028#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
Marian Balakowicz991425f2006-03-14 16:24:38 +010029void ddr_enable_ecc(unsigned int dram_size);
30#endif
31
32int board_early_init_f (void)
33{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010035
36 /* Enable flash write */
37 bcsr[1] &= ~0x01;
38
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
Kumar Gala8fe9bf62006-04-20 13:45:32 -050040 /* Use USB PHY on SYS board */
41 bcsr[5] |= 0x02;
42#endif
43
Marian Balakowicz991425f2006-03-14 16:24:38 +010044 return 0;
45}
46
47#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
48
Becky Bruce9973e3c2008-06-09 16:03:40 -050049phys_size_t initdram (int board_type)
Marian Balakowicz991425f2006-03-14 16:24:38 +010050{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
York Sund4b91062011-08-26 11:32:45 -070052 phys_size_t msize = 0;
Marian Balakowicz991425f2006-03-14 16:24:38 +010053
54 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
55 return -1;
56
57 /* DDR SDRAM - Main SODIMM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010059#if defined(CONFIG_SPD_EEPROM)
York Sun5614e712013-09-30 09:22:09 -070060#ifndef CONFIG_SYS_FSL_DDR2
York Sund4b91062011-08-26 11:32:45 -070061 msize = spd_sdram() * 1024 * 1024;
62#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
63 ddr_enable_ecc(msize);
64#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +010065#else
York Sund4b91062011-08-26 11:32:45 -070066 msize = fsl_ddr_sdram();
67#endif
68#else
69 msize = fixed_sdram() * 1024 * 1024;
Marian Balakowicz991425f2006-03-14 16:24:38 +010070#endif
71 /*
72 * Initialize SDRAM if it is on local bus.
73 */
74 sdram_init();
75
Marian Balakowicz991425f2006-03-14 16:24:38 +010076 /* return total bus SDRAM size(bytes) -- DDR */
York Sund4b91062011-08-26 11:32:45 -070077 return msize;
Marian Balakowicz991425f2006-03-14 16:24:38 +010078}
79
80#if !defined(CONFIG_SPD_EEPROM)
81/*************************************************************************
82 * fixed sdram init -- doesn't use serial presence detect.
83 ************************************************************************/
84int fixed_sdram(void)
85{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Joe Hershberger2e651b22011-10-11 23:57:31 -050087 u32 msize = CONFIG_SYS_DDR_SIZE;
88 u32 ddr_size = msize << 20; /* DDR size in bytes */
89 u32 ddr_size_log2 = __ilog2(ddr_size);
Marian Balakowicz991425f2006-03-14 16:24:38 +010090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Marian Balakowicz991425f2006-03-14 16:24:38 +010092 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#if (CONFIG_SYS_DDR_SIZE != 256)
Marian Balakowicz991425f2006-03-14 16:24:38 +010095#warning Currenly any ddr size other than 256 is not supported
96#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +080097#ifdef CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
99 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
100 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
101 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
102 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
103 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
104 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
105 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
106 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
107 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
108 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
109 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800110#else
Joe Hershberger2e651b22011-10-11 23:57:31 -0500111
112#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
113#warning Chip select bounds is only configurable in 16MB increments
114#endif
115 im->ddr.csbnds[2].csbnds =
116 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
117 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
118 CSBNDS_EA_SHIFT) & CSBNDS_EA);
119 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100120
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200121 /* currently we use only one CS, so disable the other banks */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100122 im->ddr.cs_config[0] = 0;
123 im->ddr.cs_config[1] = 0;
124 im->ddr.cs_config[3] = 0;
125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
127 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200128
Marian Balakowicz991425f2006-03-14 16:24:38 +0100129 im->ddr.sdram_cfg =
130 SDRAM_CFG_SREN
131#if defined(CONFIG_DDR_2T_TIMING)
132 | SDRAM_CFG_2T_EN
133#endif
134 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100135#if defined (CONFIG_DDR_32BIT)
136 /* for 32-bit mode burst length is 8 */
137 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
138#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800142#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100143 udelay(200);
144
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100145 /* enable DDR controller */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100146 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100147 return msize;
148}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#endif/*!CONFIG_SYS_SPD_EEPROM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100150
151
152int checkboard (void)
153{
Ira W. Snyder447ad572008-08-22 11:00:15 -0700154 /*
155 * Warning: do not read the BCSR registers here
156 *
157 * There is a timing bug in the 8349E and 8349EA BCSR code
158 * version 1.2 (read from BCSR 11) that will cause the CFI
159 * flash initialization code to overwrite BCSR 0, disabling
160 * the serial ports and gigabit ethernet
161 */
162
Marian Balakowicz991425f2006-03-14 16:24:38 +0100163 puts("Board: Freescale MPC8349EMDS\n");
164 return 0;
165}
166
Marian Balakowicz991425f2006-03-14 16:24:38 +0100167/*
168 * if MPC8349EMDS is soldered with SDRAM
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#if defined(CONFIG_SYS_BR2_PRELIM) \
171 && defined(CONFIG_SYS_OR2_PRELIM) \
172 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
173 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100174/*
175 * Initialize SDRAM memory on the Local Bus.
176 */
177
178void sdram_init(void)
179{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500181 volatile fsl_lbc_t *lbc = &immap->im_lbc;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100183
Marian Balakowicz991425f2006-03-14 16:24:38 +0100184 /*
185 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
186 */
187
188 /* setup mtrpt, lsrt and lbcr for LB bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
190 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
191 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100192 asm("sync");
193
194 /*
195 * Configure the SDRAM controller Machine Mode Register.
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100200 asm("sync");
201 *sdram_addr = 0xff;
202 udelay(100);
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100205 asm("sync");
206 /*1 times*/
207 *sdram_addr = 0xff;
208 udelay(100);
209 /*2 times*/
210 *sdram_addr = 0xff;
211 udelay(100);
212 /*3 times*/
213 *sdram_addr = 0xff;
214 udelay(100);
215 /*4 times*/
216 *sdram_addr = 0xff;
217 udelay(100);
218 /*5 times*/
219 *sdram_addr = 0xff;
220 udelay(100);
221 /*6 times*/
222 *sdram_addr = 0xff;
223 udelay(100);
224 /*7 times*/
225 *sdram_addr = 0xff;
226 udelay(100);
227 /*8 times*/
228 *sdram_addr = 0xff;
229 udelay(100);
230
231 /* 0x58636733; mode register write operation */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100233 asm("sync");
234 *sdram_addr = 0xff;
235 udelay(100);
236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100238 asm("sync");
239 *sdram_addr = 0xff;
240 udelay(100);
241}
242#else
243void sdram_init(void)
244{
Marian Balakowicz991425f2006-03-14 16:24:38 +0100245}
246#endif
Marian Balakowiczd326f4a2006-03-16 15:19:35 +0100247
Ben Warren80ddd222008-01-16 22:37:42 -0500248/*
249 * The following are used to control the SPI chip selects for the SPI command.
250 */
Ben Warrenf8cc3122008-06-08 23:28:33 -0700251#ifdef CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500252
253#define SPI_CS_MASK 0x80000000
254
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200255int spi_cs_is_valid(unsigned int bus, unsigned int cs)
256{
257 return bus == 0 && cs == 0;
258}
259
260void spi_cs_activate(struct spi_slave *slave)
Ben Warren80ddd222008-01-16 22:37:42 -0500261{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
Ben Warren80ddd222008-01-16 22:37:42 -0500263
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200264 iopd->dat &= ~SPI_CS_MASK;
Ben Warren80ddd222008-01-16 22:37:42 -0500265}
266
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200267void spi_cs_deactivate(struct spi_slave *slave)
268{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
Ben Warren80ddd222008-01-16 22:37:42 -0500270
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200271 iopd->dat |= SPI_CS_MASK;
272}
Ben Warren80ddd222008-01-16 22:37:42 -0500273#endif /* CONFIG_HARD_SPI */
274
Kim Phillips3fde9e82007-08-15 22:30:33 -0500275#if defined(CONFIG_OF_BOARD_SETUP)
276void ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600277{
Kim Phillips3fde9e82007-08-15 22:30:33 -0500278 ft_cpu_setup(blob, bd);
279#ifdef CONFIG_PCI
280 ft_pci_setup(blob, bd);
281#endif
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600282}
283#endif