Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sandeep Paulraj | 840f892 | 2010-12-28 15:43:16 -0500 | [diff] [blame] | 2 | /* |
| 3 | * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board. |
| 4 | * |
| 5 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
Sandeep Paulraj | 840f892 | 2010-12-28 15:43:16 -0500 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <net.h> |
| 10 | #include <miiphy.h> |
| 11 | #include <asm/arch/emac_defs.h> |
Masahiro Yamada | 601fbec | 2015-02-20 17:04:05 +0900 | [diff] [blame] | 12 | #include "../../../drivers/net/davinci_emac.h" |
Sandeep Paulraj | 840f892 | 2010-12-28 15:43:16 -0500 | [diff] [blame] | 13 | |
| 14 | #ifdef CONFIG_DRIVER_TI_EMAC |
| 15 | |
| 16 | #ifdef CONFIG_CMD_NET |
| 17 | |
| 18 | /* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */ |
| 19 | |
| 20 | #define MII_PHY_CONFIG_REG 22 |
| 21 | |
| 22 | /* PHY Config bits */ |
| 23 | #define PHY_SYS_CLK_EN (1 << 4) |
| 24 | |
| 25 | int et1011c_get_link_speed(int phy_addr) |
| 26 | { |
| 27 | u_int16_t data; |
| 28 | |
| 29 | if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { |
Manjunath Hadli | fb1d633 | 2011-10-13 03:40:55 +0000 | [diff] [blame] | 30 | davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data); |
Sandeep Paulraj | 840f892 | 2010-12-28 15:43:16 -0500 | [diff] [blame] | 31 | /* Enable 125MHz clock sourced from PHY */ |
Manjunath Hadli | fb1d633 | 2011-10-13 03:40:55 +0000 | [diff] [blame] | 32 | davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG, |
Sandeep Paulraj | 840f892 | 2010-12-28 15:43:16 -0500 | [diff] [blame] | 33 | data | PHY_SYS_CLK_EN); |
| 34 | return (1); |
| 35 | } |
| 36 | return (0); |
| 37 | } |
| 38 | |
| 39 | #endif /* CONFIG_CMD_NET */ |
| 40 | |
| 41 | #endif /* CONFIG_DRIVER_ETHER */ |