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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
wdenk4a9cbbe2002-08-27 09:48:53 +000010 */
11
12/*
13 * CPU specific code
14 */
15
16#include <common.h>
17#include <command.h>
Simon Glass9edefc22019-11-14 12:57:37 -070018#include <cpu_func.h>
Simon Glass36bf4462019-11-14 12:57:42 -070019#include <irq_func.h>
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020020#include <asm/system.h>
Albert ARIBAUDcd6cc342014-04-15 16:13:48 +020021#include <asm/io.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000022
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020023static void cache_flush(void);
24
wdenk4a9cbbe2002-08-27 09:48:53 +000025int cleanup_before_linux (void)
26{
27 /*
28 * this function is called just before we call linux
29 * it prepares the processor for linux
30 *
31 * just disable everything that can disturb booting linux
32 */
33
Simon Glass9d3915b2019-11-14 12:57:40 -070034 disable_interrupts();
wdenk4a9cbbe2002-08-27 09:48:53 +000035
36 /* turn off I-cache */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020037 icache_disable();
38 dcache_disable();
wdenk4a9cbbe2002-08-27 09:48:53 +000039
40 /* flush I-cache */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020041 cache_flush();
wdenk4a9cbbe2002-08-27 09:48:53 +000042
43 return (0);
44}
45
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020046/* flush I/D-cache */
47static void cache_flush (void)
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020048{
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020049 unsigned long i = 0;
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020050
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020051 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
wdenk4a9cbbe2002-08-27 09:48:53 +000052}
Albert ARIBAUDcd6cc342014-04-15 16:13:48 +020053
54#define RST_BASE 0x90030000
55#define RSRR 0x00
56#define RCSR 0x04
57
58__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
59{
60 /* repeat endlessly */
61 while (1) {
62 writel(0, RST_BASE + RCSR);
63 writel(1, RST_BASE + RSRR);
64 }
65}