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Stefan Roese0299c902015-10-20 15:14:47 +02001/*
2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
3 *
4 * Copyright (C) 2015 Russell King
5 *
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board. Things will change, don't expect this file to
9 * remain compatible info the future.
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include <dt-bindings/input/input.h>
51#include <dt-bindings/gpio/gpio.h>
52#include "armada-388.dtsi"
Baruch Siacha4adb1f2018-06-14 18:17:52 +030053#include "armada-38x-solidrun-microsom.dtsi"
Stefan Roese0299c902015-10-20 15:14:47 +020054
55/ {
56 model = "SolidRun Clearfog A1";
57 compatible = "solidrun,clearfog-a1", "marvell,armada388",
58 "marvell,armada385", "marvell,armada380";
59
60 aliases {
61 /* So that mvebu u-boot can update the MAC addresses */
62 ethernet1 = &eth0;
63 ethernet2 = &eth1;
64 ethernet3 = &eth2;
Baruch Siach8c1ce922017-11-13 07:04:31 +020065 spi1 = &spi1;
Jon Nettleton4ea813d2018-05-28 19:10:30 +030066 i2c0 = &i2c0;
67 i2c1 = &i2c1;
Stefan Roese0299c902015-10-20 15:14:47 +020068 };
69
70 chosen {
71 stdout-path = "serial0:115200n8";
72 };
73
Stefan Roese0299c902015-10-20 15:14:47 +020074 reg_3p3v: regulator-3p3v {
75 compatible = "regulator-fixed";
76 regulator-name = "3P3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-always-on;
80 };
81
82 soc {
Stefan Roese0299c902015-10-20 15:14:47 +020083 internal-regs {
Stefan Roese0299c902015-10-20 15:14:47 +020084 rtc@a3800 {
85 /*
86 * If the rtc doesn't work, run "date reset"
87 * twice in u-boot.
88 */
89 status = "okay";
90 };
91
92 sata@a8000 {
93 /* pinctrl? */
94 status = "okay";
95 };
96
97 sata@e0000 {
98 /* pinctrl? */
99 status = "okay";
100 };
101
102 sdhci@d8000 {
103 bus-width = <4>;
104 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
105 no-1-8-v;
Baruch Siacha4adb1f2018-06-14 18:17:52 +0300106 pinctrl-0 = <&microsom_sdhci_pins
Stefan Roese0299c902015-10-20 15:14:47 +0200107 &clearfog_sdhci_cd_pins>;
108 pinctrl-names = "default";
109 status = "okay";
110 vmmc = <&reg_3p3v>;
111 wp-inverted;
112 };
113
Stefan Roese0299c902015-10-20 15:14:47 +0200114 serial@12100 {
115 /* mikrobus uart */
116 pinctrl-0 = <&mikro_uart_pins>;
117 pinctrl-names = "default";
118 status = "okay";
119 };
120
Chris Packham30c43832018-12-10 20:07:51 +1300121 usb3@f8000 {
Jon Nettleton334eebe2018-06-14 18:17:53 +0300122 /* CON7, USB-A port on back of device */
Stefan Roese0299c902015-10-20 15:14:47 +0200123 status = "okay";
124 };
125 };
126
Chris Packham825dd502019-03-16 20:46:20 +1300127 pcie {
Stefan Roese0299c902015-10-20 15:14:47 +0200128 status = "okay";
129 /*
130 * The two PCIe units are accessible through
131 * the mini-PCIe connectors on the board.
132 */
133 pcie@2,0 {
134 /* Port 1, Lane 0. CONN3, nearest power. */
135 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
136 status = "okay";
137 };
138 pcie@3,0 {
139 /* Port 2, Lane 0. CONN2, nearest CPU. */
140 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
141 status = "okay";
142 };
143 };
144 };
145
Stefan Roese0299c902015-10-20 15:14:47 +0200146 gpio-keys {
147 compatible = "gpio-keys";
148 pinctrl-0 = <&rear_button_pins>;
149 pinctrl-names = "default";
150
151 button_0 {
152 /* The rear SW3 button */
153 label = "Rear Button";
154 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
155 linux,can-disable;
156 linux,code = <BTN_0>;
157 };
158 };
159};
160
Baruch Siacha4adb1f2018-06-14 18:17:52 +0300161&w25q32 {
162 status = "okay";
163};
164
Jon Nettleton334eebe2018-06-14 18:17:53 +0300165&eth1 {
166 managed = "in-band-status";
167 phy-mode = "sgmii";
168 status = "okay";
169};
170
171&eth2 {
172 phy-mode = "sgmii";
173 status = "okay";
174};
175
176&i2c0 {
177 clock-frequency = <400000>;
178 pinctrl-0 = <&i2c0_pins>;
179 pinctrl-names = "default";
180 status = "okay";
181
182 /*
183 * PCA9655 GPIO expander, up to 1MHz clock.
184 * 0-CON3 CLKREQ#
185 * 1-CON3 PERST#
186 * 2-CON2 PERST#
187 * 3-CON3 W_DISABLE
188 * 4-CON2 CLKREQ#
189 * 5-USB3 overcurrent
190 * 6-USB3 power
191 * 7-CON2 W_DISABLE
192 * 8-JP4 P1
193 * 9-JP4 P4
194 * 10-JP4 P5
195 * 11-m.2 DEVSLP
196 * 12-SFP_LOS
197 * 13-SFP_TX_FAULT
198 * 14-SFP_TX_DISABLE
199 * 15-SFP_MOD_DEF0
200 */
201 expander0: gpio-expander@20 {
202 /*
203 * This is how it should be:
204 * compatible = "onnn,pca9655",
205 * "nxp,pca9555";
206 * but you can't do this because of
207 * the way I2C works.
208 */
209 compatible = "nxp,pca9555";
210 gpio-controller;
211 #gpio-cells = <2>;
212 reg = <0x20>;
213
214 pcie1_0_clkreq {
215 gpio-hog;
216 gpios = <0 GPIO_ACTIVE_LOW>;
217 input;
218 line-name = "pcie1.0-clkreq";
219 };
220 pcie1_0_w_disable {
221 gpio-hog;
222 gpios = <3 GPIO_ACTIVE_LOW>;
223 output-low;
224 line-name = "pcie1.0-w-disable";
225 };
226 pcie2_0_clkreq {
227 gpio-hog;
228 gpios = <4 GPIO_ACTIVE_LOW>;
229 input;
230 line-name = "pcie2.0-clkreq";
231 };
232 pcie2_0_w_disable {
233 gpio-hog;
234 gpios = <7 GPIO_ACTIVE_LOW>;
235 output-low;
236 line-name = "pcie2.0-w-disable";
237 };
238 usb3_ilimit {
239 gpio-hog;
240 gpios = <5 GPIO_ACTIVE_LOW>;
241 input;
242 line-name = "usb3-current-limit";
243 };
244 usb3_power {
245 gpio-hog;
246 gpios = <6 GPIO_ACTIVE_HIGH>;
247 output-high;
248 line-name = "usb3-power";
249 };
250 m2_devslp {
251 gpio-hog;
252 gpios = <11 GPIO_ACTIVE_HIGH>;
253 output-low;
254 line-name = "m.2 devslp";
255 };
256 };
257
258 mikrobus_adc: mcp3021@4c {
259 compatible = "microchip,mcp3021";
260 reg = <0x4c>;
261 };
262};
263
264&i2c1 {
265 /*
266 * Routed to SFP, mikrobus, and PCIe.
267 * SFP limits this to 100kHz, and requires
268 * an AT24C01A/02/04 with address pins tied
269 * low, which takes addresses 0x50 and 0x51.
270 * Mikrobus doesn't specify beyond an I2C
271 * bus being present.
272 * PCIe uses ARP to assign addresses, or
273 * 0x63-0x64.
274 */
275 clock-frequency = <100000>;
276 pinctrl-0 = <&clearfog_i2c1_pins>;
277 pinctrl-names = "default";
278 status = "okay";
279};
280
281&pinctrl {
282 clearfog_i2c1_pins: i2c1-pins {
283 /* SFP, PCIe, mSATA, mikrobus */
284 marvell,pins = "mpp26", "mpp27";
285 marvell,function = "i2c1";
286 };
287 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
288 marvell,pins = "mpp20";
289 marvell,function = "gpio";
290 };
291 clearfog_spi1_cs_pins: spi1-cs-pins {
292 marvell,pins = "mpp55";
293 marvell,function = "spi1";
294 };
295 mikro_pins: mikro-pins {
296 /* int: mpp22 rst: mpp29 */
297 marvell,pins = "mpp22", "mpp29";
298 marvell,function = "gpio";
299 };
300 mikro_spi_pins: mikro-spi-pins {
301 marvell,pins = "mpp43";
302 marvell,function = "spi1";
303 };
304 mikro_uart_pins: mikro-uart-pins {
305 marvell,pins = "mpp24", "mpp25";
306 marvell,function = "ua1";
307 };
308 rear_button_pins: rear-button-pins {
309 marvell,pins = "mpp34";
310 marvell,function = "gpio";
311 };
312};
313
Chris Packham30c43832018-12-10 20:07:51 +1300314&spi1 {
315 /*
316 * Add SPI CS pins for clearfog:
317 * CS0: W25Q32
318 * CS1:
319 * CS2: mikrobus
320 */
321 pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
322 pinctrl-names = "default";
323 status = "okay";
324};
325
Stefan Roese0299c902015-10-20 15:14:47 +0200326/*
327+#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
328MPP18: gpio ? (pca9655 int?)
329MPP19: gpio ? (clkreq?)
330MPP20: gpio ? (sd0 detect)
331MPP21: sd0:cmd x sd0
332MPP22: gpio x mikro int
333MPP23: gpio x switch irq
334+#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
335MPP24: ua1:rxd x mikro rx
336MPP25: ua1:txd x mikro tx
337MPP26: i2c1:sck x mikro sck
338MPP27: i2c1:sda x mikro sda
339MPP28: sd0:clk x sd0
340MPP29: gpio x mikro rst
341MPP30: ge1:txd2 ? (config)
342MPP31: ge1:txd3 ? (config)
343+#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
344MPP32: ge1:txctl ? (unused)
345MPP33: gpio ? (pic_com0)
346MPP34: gpio x rear button (pic_com1)
347MPP35: gpio ? (pic_com2)
348MPP36: gpio ? (unused)
349MPP37: sd0:d3 x sd0
350MPP38: sd0:d0 x sd0
351MPP39: sd0:d1 x sd0
352+#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
353MPP40: sd0:d2 x sd0
354MPP41: gpio x switch reset
355MPP42: gpio ? sw1-1
356MPP43: spi1:cs2 x mikro cs
357MPP44: sata3:prsnt ? (unused)
358MPP45: ref:clk_out0 ?
359MPP46: ref:clk_out1 x switch clk
360MPP47: 4 ? (unused)
361+#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
362MPP48: tdm:pclk
363MPP49: tdm:fsync
364MPP50: tdm:drx
365MPP51: tdm:dtx
366MPP52: tdm:int
367MPP53: tdm:rst
368MPP54: gpio ? (pwm)
369MPP55: spi1:cs1 x slic
370+#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
371MPP56: spi1:mosi x mikro mosi
372MPP57: spi1:sck x mikro sck
373MPP58: spi1:miso x mikro miso
374MPP59: spi1:cs0 x w25q32
375*/