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Haavard Skinnemoen6b443942007-04-14 17:11:49 +02001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen6b443942007-04-14 17:11:49 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020012
Andreas Bießmannb78431a2011-04-18 04:12:35 +000013#define CONFIG_AT32AP
14#define CONFIG_AT32AP7000
15#define CONFIG_ATNGW100
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020016
Andreas Bießmannfb1e3eb2015-05-23 23:09:15 +020017#define CONFIG_BOARD_EARLY_INIT_F
18#define CONFIG_BOARD_EARLY_INIT_R
19
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020020/*
21 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
22 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
23 * and the PBA bus to run at 1/4 the PLL frequency.
24 */
Andreas Bießmannb78431a2011-04-18 04:12:35 +000025#define CONFIG_PLL
26#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_OSC0_HZ 20000000
28#define CONFIG_SYS_PLL0_DIV 1
29#define CONFIG_SYS_PLL0_MUL 7
30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
31#define CONFIG_SYS_CLKDIV_CPU 0
32#define CONFIG_SYS_CLKDIV_HSB 1
33#define CONFIG_SYS_CLKDIV_PBA 2
34#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020035
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070036/* Reserve VM regions for SDRAM and NOR flash */
37#define CONFIG_SYS_NR_VM_REGIONS 2
38
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020039/*
40 * The PLLOPT register controls the PLL like this:
41 * icp = PLLOPT<2>
42 * ivco = PLLOPT<1:0>
43 *
44 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
45 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020047
Andreas Bießmannf4278b72010-11-04 23:15:31 +000048#define CONFIG_USART_BASE ATMEL_BASE_USART1
49#define CONFIG_USART_ID 1
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020050/* User serviceable stuff */
Andreas Bießmannb78431a2011-04-18 04:12:35 +000051#define CONFIG_DOS_PARTITION
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020052
Andreas Bießmannb78431a2011-04-18 04:12:35 +000053#define CONFIG_CMDLINE_TAG
54#define CONFIG_SETUP_MEMORY_TAGS
55#define CONFIG_INITRD_TAG
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020056
57#define CONFIG_STACKSIZE (2048)
58
59#define CONFIG_BAUDRATE 115200
60#define CONFIG_BOOTARGS \
61 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
62#define CONFIG_BOOTCOMMAND \
63 "fsload; bootm"
64
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020065#define CONFIG_BOOTDELAY 1
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020066
67/*
68 * After booting the board for the first time, new ethernet addresses
69 * should be generated and assigned to the environment variables
70 * "ethaddr" and "eth1addr". This is normally done during production.
71 */
Andreas Bießmannb78431a2011-04-18 04:12:35 +000072#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020073
74/*
75 * BOOTP/DHCP options
76 */
77#define CONFIG_BOOTP_SUBNETMASK
78#define CONFIG_BOOTP_GATEWAY
79
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020080/*
81 * Command line configuration.
82 */
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020083#define CONFIG_CMD_ASKENV
84#define CONFIG_CMD_DHCP
85#define CONFIG_CMD_EXT2
86#define CONFIG_CMD_FAT
87#define CONFIG_CMD_JFFS2
88#define CONFIG_CMD_MMC
Haavard Skinnemoen5f723a32008-06-20 10:41:05 +020089#define CONFIG_CMD_SF
90#define CONFIG_CMD_SPI
David Brownell55ac7a72008-02-22 12:54:39 -080091
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020092
Andreas Bießmannb78431a2011-04-18 04:12:35 +000093#define CONFIG_ATMEL_USART
94#define CONFIG_MACB
95#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmannb78431a2011-04-18 04:12:35 +000097#define CONFIG_SYS_HSDRAMC
98#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +020099#define CONFIG_GENERIC_ATMEL_MCI
100#define CONFIG_GENERIC_MMC
Andreas Bießmannb78431a2011-04-18 04:12:35 +0000101#define CONFIG_ATMEL_SPI
Haavard Skinnemoen5f723a32008-06-20 10:41:05 +0200102
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DCACHE_LINESZ 32
105#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200106
107#define CONFIG_NR_DRAM_BANKS 1
108
Andreas Bießmannb78431a2011-04-18 04:12:35 +0000109#define CONFIG_SYS_FLASH_CFI
110#define CONFIG_FLASH_CFI_DRIVER
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BASE 0x00000000
113#define CONFIG_SYS_FLASH_SIZE 0x800000
114#define CONFIG_SYS_MAX_FLASH_BANKS 1
115#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmannda484372011-04-18 04:12:43 +0000118#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
121#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
122#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200123
Andreas Bießmannb78431a2011-04-18 04:12:35 +0000124#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200125#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200131
132/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
134#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200135
136/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_CBSIZE 256
138#define CONFIG_SYS_MAXARGS 16
139#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmannb78431a2011-04-18 04:12:35 +0000140#define CONFIG_SYS_LONGHELP
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
143#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Haavard Skinnemoen2bcacc22007-11-22 16:51:39 +0100144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200146
147#endif /* __CONFIG_H */