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Bo Shen3225f342013-05-12 22:40:54 +00001/*
2 * Configuation settings for the SAMA5D3xEK board.
3 *
4 * Copyright (C) 2012 - 2013 Atmel
5 *
6 * based on at91sam9m10g45ek.h by:
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Bo Shen3225f342013-05-12 22:40:54 +000011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Wu, Joshb2d387b2015-03-30 14:51:19 +080016/*
17 * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
18 * before the common header.
19 */
20#include "at91-sama5_common.h"
Bo Shen3225f342013-05-12 22:40:54 +000021
Wu, Josh89a36582015-08-19 19:11:19 +080022#define CONFIG_BOARD_LATE_INIT
23#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
24
Bo Shen3225f342013-05-12 22:40:54 +000025/* serial console */
26#define CONFIG_ATMEL_USART
27#define CONFIG_USART_BASE ATMEL_BASE_DBGU
28#define CONFIG_USART_ID ATMEL_ID_DBGU
29
30/*
31 * This needs to be defined for the OHCI code to work but it is defined as
32 * ATMEL_ID_UHPHS in the CPU specific header files.
33 */
34#define ATMEL_ID_UHP ATMEL_ID_UHPHS
35
36/*
37 * Specify the clock enable bit in the PMC_SCER register.
38 */
39#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
40
41/* LCD */
42#define CONFIG_LCD
43#define LCD_BPP LCD_COLOR16
44#define LCD_OUTPUT_BPP 24
45#define CONFIG_LCD_LOGO
Bo Shen3225f342013-05-12 22:40:54 +000046#define CONFIG_LCD_INFO
47#define CONFIG_LCD_INFO_BELOW_LOGO
48#define CONFIG_SYS_WHITE_ON_BLACK
49#define CONFIG_ATMEL_HLCD
50#define CONFIG_ATMEL_LCD_RGB565
51#define CONFIG_SYS_CONSOLE_IS_IN_ENV
52
53/* board specific (not enough SRAM) */
54#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
55
Bo Shend6b79432014-07-18 16:43:08 +080056/* NOR flash */
Wu, Joshb2d387b2015-03-30 14:51:19 +080057#ifndef CONFIG_SYS_NO_FLASH
Bo Shend6b79432014-07-18 16:43:08 +080058#define CONFIG_FLASH_CFI_DRIVER
59#define CONFIG_SYS_FLASH_CFI
60#define CONFIG_SYS_FLASH_PROTECTION
61#define CONFIG_SYS_FLASH_BASE 0x10000000
62#define CONFIG_SYS_MAX_FLASH_SECT 131
63#define CONFIG_SYS_MAX_FLASH_BANKS 1
Bo Shend6b79432014-07-18 16:43:08 +080064#endif
Bo Shen3225f342013-05-12 22:40:54 +000065
Bo Shen3225f342013-05-12 22:40:54 +000066/* SDRAM */
67#define CONFIG_NR_DRAM_BANKS 1
68#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
69#define CONFIG_SYS_SDRAM_SIZE 0x20000000
70
Bo Shenc5e88852013-11-15 11:12:38 +080071#ifdef CONFIG_SPL_BUILD
72#define CONFIG_SYS_INIT_SP_ADDR 0x310000
73#else
Bo Shen3225f342013-05-12 22:40:54 +000074#define CONFIG_SYS_INIT_SP_ADDR \
75 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenc5e88852013-11-15 11:12:38 +080076#endif
Bo Shen3225f342013-05-12 22:40:54 +000077
78/* SerialFlash */
79#define CONFIG_CMD_SF
80
81#ifdef CONFIG_CMD_SF
82#define CONFIG_ATMEL_SPI
Bo Shen3225f342013-05-12 22:40:54 +000083#define CONFIG_SF_DEFAULT_SPEED 30000000
84#endif
85
86/* NAND flash */
87#define CONFIG_CMD_NAND
88
89#ifdef CONFIG_CMD_NAND
Bo Shen3225f342013-05-12 22:40:54 +000090#define CONFIG_NAND_ATMEL
91#define CONFIG_SYS_MAX_NAND_DEVICE 1
92#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
93/* our ALE is AD21 */
94#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
95/* our CLE is AD22 */
96#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
97#define CONFIG_SYS_NAND_ONFI_DETECTION
98/* PMECC & PMERRLOC */
99#define CONFIG_ATMEL_NAND_HWECC
100#define CONFIG_ATMEL_NAND_HW_PMECC
101#define CONFIG_PMECC_CAP 4
102#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen3225f342013-05-12 22:40:54 +0000103#define CONFIG_CMD_NAND_TRIMFFS
104#endif
105
106/* Ethernet Hardware */
107#define CONFIG_MACB
108#define CONFIG_RMII
Bo Shen3225f342013-05-12 22:40:54 +0000109#define CONFIG_NET_RETRY_COUNT 20
110#define CONFIG_MACB_SEARCH_PHY
Bo Shene08d6f32013-06-26 10:11:06 +0800111#define CONFIG_RGMII
112#define CONFIG_CMD_MII
113#define CONFIG_PHYLIB
114#define CONFIG_PHY_MICREL
115#define CONFIG_PHY_MICREL_KSZ9021
Bo Shen3225f342013-05-12 22:40:54 +0000116
117/* MMC */
118#define CONFIG_CMD_MMC
119
120#ifdef CONFIG_CMD_MMC
121#define CONFIG_MMC
122#define CONFIG_GENERIC_MMC
123#define CONFIG_GENERIC_ATMEL_MCI
124#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
125#endif
126
127/* USB */
128#define CONFIG_CMD_USB
129
130#ifdef CONFIG_CMD_USB
131#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800132#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen3225f342013-05-12 22:40:54 +0000133#define CONFIG_USB_OHCI_NEW
134#define CONFIG_SYS_USB_OHCI_CPU_INIT
135#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
136#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
137#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
138#define CONFIG_DOS_PARTITION
139#define CONFIG_USB_STORAGE
140#endif
141
Bo Shen3668ce32013-09-11 18:24:51 +0800142/* USB device */
143#define CONFIG_USB_GADGET
144#define CONFIG_USB_GADGET_DUALSPEED
145#define CONFIG_USB_GADGET_ATMEL_USBA
146#define CONFIG_USB_ETHER
147#define CONFIG_USB_ETH_RNDIS
148#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
149
Bo Shen3225f342013-05-12 22:40:54 +0000150#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
151#define CONFIG_CMD_FAT
Wu, Josha2485582015-01-20 10:33:32 +0800152#define CONFIG_FAT_WRITE
Bo Shen3225f342013-05-12 22:40:54 +0000153#endif
154
155#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
156
157#ifdef CONFIG_SYS_USE_SERIALFLASH
Wu, Josh7a53b952015-08-19 19:11:21 +0800158/* override the bootcmd, bootargs and other configuration for spi flash env*/
Bo Shen3225f342013-05-12 22:40:54 +0000159#elif CONFIG_SYS_USE_NANDFLASH
Wu, Joshdc018fe2015-08-19 19:11:20 +0800160/* override the bootcmd, bootargs and other configuration nandflash env */
Bo Shen3225f342013-05-12 22:40:54 +0000161#elif CONFIG_SYS_USE_MMC
Wu, Josh372ca032015-08-19 19:11:18 +0800162/* override the bootcmd, bootargs and other configuration for sd/mmc env */
Bo Shen3225f342013-05-12 22:40:54 +0000163#else
Bo Shena4c79b32013-08-11 14:26:20 +0000164#define CONFIG_ENV_IS_NOWHERE
Bo Shen3225f342013-05-12 22:40:54 +0000165#endif
166
Bo Shenc5e88852013-11-15 11:12:38 +0800167/* SPL */
Bo Shenc5e88852013-11-15 11:12:38 +0800168#define CONFIG_SPL_FRAMEWORK
169#define CONFIG_SPL_TEXT_BASE 0x300000
170#define CONFIG_SPL_MAX_SIZE 0x10000
171#define CONFIG_SPL_BSS_START_ADDR 0x20000000
172#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
173#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
174#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
175
176#define CONFIG_SPL_LIBCOMMON_SUPPORT
177#define CONFIG_SPL_LIBGENERIC_SUPPORT
178#define CONFIG_SPL_GPIO_SUPPORT
179#define CONFIG_SPL_SERIAL_SUPPORT
180
181#define CONFIG_SPL_BOARD_INIT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800182#define CONFIG_SYS_MONITOR_LEN (512 << 10)
183
Bo Shenc5e88852013-11-15 11:12:38 +0800184#ifdef CONFIG_SYS_USE_MMC
Bo Shen993ea972015-03-04 13:32:57 +0800185#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
Bo Shenc5e88852013-11-15 11:12:38 +0800186#define CONFIG_SPL_MMC_SUPPORT
187#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
188#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100189#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200190#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shenc5e88852013-11-15 11:12:38 +0800191#define CONFIG_SPL_FAT_SUPPORT
192#define CONFIG_SPL_LIBDISK_SUPPORT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800193
Bo Shen27019e42014-03-03 14:47:17 +0800194#elif CONFIG_SYS_USE_NANDFLASH
195#define CONFIG_SPL_NAND_SUPPORT
196#define CONFIG_SPL_NAND_DRIVERS
197#define CONFIG_SPL_NAND_BASE
198#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
199#define CONFIG_SYS_NAND_5_ADDR_CYCLE
200#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
201#define CONFIG_SYS_NAND_PAGE_COUNT 64
202#define CONFIG_SYS_NAND_OOBSIZE 64
203#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
204#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Andreas Bießmanne166a832014-05-19 14:23:41 +0200205#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
Bo Shen27019e42014-03-03 14:47:17 +0800206
Bo Shen8a45b0b2014-03-03 14:47:15 +0800207#elif CONFIG_SYS_USE_SERIALFLASH
208#define CONFIG_SPL_SPI_SUPPORT
209#define CONFIG_SPL_SPI_FLASH_SUPPORT
210#define CONFIG_SPL_SPI_LOAD
Wu, Josh7a53b952015-08-19 19:11:21 +0800211#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Bo Shen8a45b0b2014-03-03 14:47:15 +0800212
Bo Shenc5e88852013-11-15 11:12:38 +0800213#endif
214
Bo Shen3225f342013-05-12 22:40:54 +0000215#endif